Hello to all
i have master Clock 40 Mhz and from master Clock want Generate 1.2 Khz Square wave pulses at output
my code is as below
(1) what is problm with my Code
(2) how Counter works and how to decide the Counter values like
these designs
(3) without Counter can we use Shift ??
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Clk_divider is
port(
resetn : in std_logic; -- Reset
MHZ_clock : in std_logic;
Out_clock : out std_logic
);
end Clk_divider;
architecture Clk_divider_arch of Clk_divider is
signal clk_count : std_logic_vector(16 downto 0) :=
"00000000000000000"; -- 16 Bit Counter
begin
Clock : process(resetn, MHZ_clock) -- 0.025uSec
begin
if(resetn = '0') then
Out_clock <= '0';
elsif(MHZ_clock'event and MHZ_clock = '1') then
if(clk_count <= "01000001000101000") then --- want Generate
Delay (40M Hz /1.2K Hz = 3320)
clk_count <= clk_count + '1';
out_clock <= '1';
elsif(( clk_count > "01000001000101000") AND (clk_count <
"10000010001010000"))then
-- 0 to 3333 ON and 3333 to 6666 OFF
out_clock <= '0';
clk_count <= clk_count + '1';
if(clk_count = "10000010001010000") then
clk_count <= "00000000000000000" ;
end if;
end if ;
end if ;
end process Clock ;
end Clk_divider_arch ;
Waiting fr replies ..
with Advance Thanks
Joshi