problem with 1.2KHz clock from 40MHz source

[joshi]

Please Help me

Hello to all

i have master Clock 40 Mhz and from master Clock want Generate 1.2 Khz Square wave pulses at output

my code is as below

(1) what is problm with my Code
(2) how Counter works and how to decide the Counter values like
these designs
(3) without Counter can we use Shift ??


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity Clk_divider is
port(
resetn : in std_logic; -- Reset
MHZ_clock : in std_logic;
Out_clock : out std_logic

);
end Clk_divider;

architecture Clk_divider_arch of Clk_divider is

signal clk_count : std_logic_vector(16 downto 0) :=
"00000000000000000"; -- 16 Bit Counter

begin

Clock : process(resetn, MHZ_clock) -- 0.025uSec
begin
if(resetn = '0') then
Out_clock <= '0';

elsif(MHZ_clock'event and MHZ_clock = '1') then
if(clk_count <= "01000001000101000") then --- want Generate
Delay (40M Hz /1.2K Hz = 3320)
clk_count <= clk_count + '1';
out_clock <= '1';

elsif(( clk_count > "01000001000101000") AND (clk_count <
"10000010001010000"))then
-- 0 to 3333 ON and 3333 to 6666 OFF

out_clock <= '0';
clk_count <= clk_count + '1';
if(clk_count = "10000010001010000") then
clk_count <= "00000000000000000" ;

end if;
end if ;

end if ;
end process Clock ;
end Clk_divider_arch ;

Waiting fr replies ..

with Advance Thanks
Joshi

 

[kvingle]

Re: Please Help me

Hello to all

i have master Clock 40 Mhz and from master Clock want Generate 1.2 Khz Square wave pulses at output

my code is as below

(1) what is problm with my Code
(2) how Counter works and how to decide the Counter values like
these designs
(3) without Counter can we use Shift ??


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity Clk_divider is
port(
resetn : in std_logic; -- Reset
MHZ_clock : in std_logic;
Out_clock : out std_logic

);
end Clk_divider;

architecture Clk_divider_arch of Clk_divider is

signal clk_count : std_logic_vector(16 downto 0) :=
"00000000000000000"; -- 16 Bit Counter

begin

Clock : process(resetn, MHZ_clock) -- 0.025uSec
begin
if(resetn = '0') then
Out_clock <= '0';

elsif(MHZ_clock'event and MHZ_clock = '1') then
if(clk_count <= "01000001000101000") then --- want Generate
Delay (40M Hz /1.2K Hz = 3320)
clk_count <= clk_count + '1';
out_clock <= '1';

elsif(( clk_count > "01000001000101000") AND (clk_count <
"10000010001010000"))then
-- 0 to 3333 ON and 3333 to 6666 OFF

out_clock <= '0';
clk_count <= clk_count + '1';
if(clk_count = "10000010001010000") then
clk_count <= "00000000000000000" ;

end if;
end if ;

end if ;
end process Clock ;
end Clk_divider_arch ;

Waiting fr replies ..

with Advance Thanks
Joshi

The statement which increments the counter variable clk_count is incremented inside a if which checks if it has reached a value.....
now assuming your counter startes from a value zero....
when exactly you hope that it will increment...?

I would suggest write

elsif(MHZ_clock'event and MHZ_clock = '1') then
clk_count <= clk_count + '1';
-----------
-- your code
-------
It should work otherwise....

Added after 12 minutes:

humm..
other thing...the code is generating a clock of 0.6 Khz...
Bcoz you are keeping output clock On for 33320 and off from 33320.
so period = 1/(33320+33320)
make it on for 16660 and off for 16660.

 

[joshi]

Re: Please Help me

Thanks lot for yur Inputs ..

ya it Should be 16660 ON and 16660 OFF
abd yur One more input
*******************
I would suggest write

elsif(MHZ_clock'event and MHZ_clock = '1') then
clk_count <= clk_count + '1';
-----------
-- your code
-------
It should work otherwise....
********************

here i want increament Counter Up to 16660 (100000100010100) and one its end counter value i want to make Counter 0000000000000000 that y i wrote code like this .Jus assume Counter 50 -->i made 0 to 25 O/P High and 25 to 50 i made O/P low ...
************************
elsif(MHZ_clock'event and MHZ_clock = '1') then
if(clk_count <= "01000001000101000") then --- want Generate Dela
--(40M Hz/1.2K Hz = 3320)

clk_count <= clk_count + '1';
out_clock <= '1';

***********************
by yur logic how can i make couner value Zero ??

one more thing i already Synthesised this Code but not abld to Simulate ...