harian
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hi,
i am new to Vhdl. I have written a test bench which read real Data from a text file,store it in a array in vhdl testbench. Then i have converted it into Std_logich vector and store this new data in another array.
I need to feed this array as Input to my testbench. I have done this with following code.
In the simulation,,In_operand0 and in_operand1 are just simulated für one vlaue of array "int0" i.e. Zero and the output is also showing just only one vlaue.
can you please help me or have any suggestion,sothat the whole elements of array be feeded at input "In_operand0 " and the output be shown related inputs for each and every element of Input array int0.
best regards
i am new to Vhdl. I have written a test bench which read real Data from a text file,store it in a array in vhdl testbench. Then i have converted it into Std_logich vector and store this new data in another array.
I need to feed this array as Input to my testbench. I have done this with following code.
Code:
type mem is array(1 to 10000) of real; --store real data
type int0 is array(1 to 10000) of std_logic_vector(11 downto 0);--store converted data binary data
signal b0:int0;--signal to feeded to intput
b0(i)<=std_logic_vector(to_unsigned( ( integer (data_in0(i)*65536.0)),12));-- converting to Std_logic_vector
--feeding the array to Input??????
for j in 1 to 10000 loop
in_operand0 <= b0(j);wait for 5 ns;
in_operand1 <= b1(j);wait for 5 ns;
b_out_1(j) <= out_result;wait for 5 ns;
end loop;
In the simulation,,In_operand0 and in_operand1 are just simulated für one vlaue of array "int0" i.e. Zero and the output is also showing just only one vlaue.
can you please help me or have any suggestion,sothat the whole elements of array be feeded at input "In_operand0 " and the output be shown related inputs for each and every element of Input array int0.
best regards