Problem when trying to increase the register width in Verilog

lorempa · Jun 29, 2011

Hi guys,

I'm a noob trying to become more and more expert
The project I'm trying to design should be able to correlate (or auto-correlate) a binary signal (i.e. an arbitrary binary sequence) and output the correlation coeffs using a 16-bit word.
All was coded under Verilog and I'm using Xilinx Spartan-6 as development board to run it.

So, now to the wear behavior.

When trying to test it sending some bytes from HTerm through serial port everything worked fine till the register which kept all the bits doesn't exceed the value of 256 bit (i.e. 16 bytes). When trying to correlate a larger sequence , like 512 bits, the values are inconsistent!!

A last clarification: the method makes a circular right shift of 1 bit of the entire sequence, then autocorrelate the signal (using XNOR and counting the numb of 1s and 0s and then finally summing the 2 sums)

Any idea? There's maybe some kind of limitation in the register width in Verilog/Xilinx FPGA?
BTW, everything works very fine when simulating the 32 bytes (or even more) testcase with ISim!

Here is the core module:

Code Verilog - [expand]
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    10:52:45 05/18/2011 
// Design Name: 
// Module Name:    magic_box16bit 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module magic_box16bit
                    #(parameter NBIT = 512    // # bits in the sequence
                        )
                       (input clk,
                         input reset,
                         input [NBIT-1:0] seq2shift,
                         input start_magic,
                         output [7:0] coeff,
                         output reg end_tick
                        );
            
                     
        // symbolic state declaration
        localparam [1:0]
            idle  = 2'b00,
            corr  = 2'b01,
            split = 2'b10;
            
        // signal declaration
        reg [1:0] state_reg, state_next;
        reg [9:0] c_reg, c_next;  // counts up to 512 bits
        reg [NBIT-1:0] b_reg, b_next;
        reg [15:0] bb_reg, bb_next;
        reg [1:0] s_reg, s_next;
 
 
 
            
        integer i;
        
        reg signed [15:0] sum;
        reg [15:0] ones, zeros;
        reg [NBIT-1:0] tmp;
        reg [NBIT-1:0] seq_ref;
        reg [7:0] c;
 
 
        // body
        // FSMD state & data registers
        always @(posedge clk, posedge reset)
            if (reset)
                begin
                    state_reg <= idle;
                    c_reg <= 0;
                    b_reg <= 0;
                    s_reg <= 0;
                    bb_reg <= 0;
                end
            else
                begin
                    state_reg <= state_next;
                    c_reg <= c_next;
                    b_reg <= b_next;
                    s_reg <= s_next;
                    bb_reg <= bb_next;
                end
            
                
        always@*
        begin
            state_next = state_reg;
            end_tick = 1'b0;
            sum = 0;
            zeros = 0;
            ones = 0;
            tmp = 0;
            c = 0;
            c_next = c_reg;
            b_next = b_reg;
            s_next = s_reg;
            bb_next = bb_reg;
            case (state_reg)
    
                
                idle:
                begin
                    if(start_magic)
                    begin
                        b_next = seq2shift;
                        state_next = corr;
                        c_next = 0;
                    end
                end
                
            
            
                corr:
                begin
                    if(c_reg == NBIT)
                        state_next = idle;
                        
                    else
                    begin
 
                        b_next = (b_reg >> 1) | (b_reg << 511); //right circular shift
                        //b_next = {b_reg[0], b_reg[NBIT-1:1]};  // barrel shifter of 1 bit left!
                        c_next = c_reg +1;
 
                        tmp = b_reg~^seq2shift;
                        for (i=0; i<NBIT; i=i+1)
                            ones = ones + tmp[i];
                        
                        zeros = NBIT - ones;
 
                        sum = ones - zeros;
                        bb_next = sum;
                        state_next = split;
                        s_next = 0;
                    end
                
                end
                
                
                split:
                begin   
                    if (s_reg == 1)
                    begin
                        c = bb_reg[7:0];
                        s_next =  s_reg + 1;
                        end_tick = 1'b1;
                        state_next = corr;
                    end
                    else
                    begin
                        c = bb_reg[15:8];
                        s_next =  s_reg + 1;
                        end_tick = 1'b1;
                    end
 
                end
                        
            endcase 
        end
        
        assign coeff = c;
 
 
endmodule

Cheers, LoREmpa

Problem when trying to increase the register width in Verilog

lorempa

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Problem when trying to increase the register width in Verilog

lorempa

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