Hi,
my name ist Tobi and i'm studying Electrical engineering.
I started to learn system verilog and i am trying to program a cyclone 2 on an EP2C5 mini board.
I use Quartus 2 13.0spi1 Web Edition. My problem is weird behaviour in a program that i wrote. It is just supposed to count the number of times
i pressed a button and display the number in binary on 3 LEDs. I have a register as the counter and a module i found on the internet that handles
the button logic. It works, but if i change the mapping between the LEDs and the counter output it doesn't work anymore
Code:
Code Verilog - [expand] |
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| module getting_pro(
input PB,
input clk,
output LED0,
output LED1,
output LED2
);
reg[2:0] counter;
//reflects state (pushed/not pushed)
wire PB_state;
//is 1 for one clock cycle if button gets pressed
wire PB_up;
//is 1 for one clock cycle if button gets released
wire PB_down;
//debouncer module i found
PushButton_Debouncer debouncer(
.clk(clk),
.PB(~PB),
.PB_state(PB_state),
.PB_up(PB_up),
.PB_down(PB_down)
);
//the not is because the LEDs are on when the Pin is 0
//The weired stuff happens here
assign LED0 = ~counter[0];
assign LED1 = ~counter[1];
assign LED2 = ~counter[2];
//if i change it to this
assign LED0 = ~counter[2];
assign LED1 = ~counter[1];
assign LED2 = ~counter[0];
//the leds blink as if counter[0] wouldn't exist
// it counts up normally and resets normally it just starts with setting counter[1]
always_ff @(posedge PB_down)
begin
//if counter smaller than 7 count up , otherwise set counter to 0
if(counter < 3'b111)
begin
counter <= counter + 3'b001;
end
else
begin
counter <= 3'b000;
end
end
endmodule |
I changed counter[2:0] to counter[0:2] and it has the same behaviour just the other way around with counter[2]
P.S. this is my first forum question. Tell me if i did something wrong