library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity g1_wbus_client_fifos_vhdl is
Port (
-- Clock and reset
i_aur_clk : IN std_logic;
i_rst : IN std_logic;
-- wbus stack interface
o_wbus_ready : OUT std_logic;
i_wbus_wen : IN std_logic;
i_wbus_addr : IN std_logic_vector(31 DOWNTO 0);
i_wbus_data : IN std_logic_vector(31 DOWNTO 0);
-- 26 Client Channels
i_wbus_enable : IN std_logic_vector(25 DOWNTO 0);
i_wbus_fws : IN std_logic_vector(129 DOWNTO 0);
i_wbus_clk : IN std_logic_vector(25 DOWNTO 0);
o_wbus_empty : OUT std_logic_vector(25 DOWNTO 0);
i_wbus_ren : IN std_logic_vector(25 DOWNTO 0);
o_wbus_count : OUT std_logic_vector(259 DOWNTO 0);
o_wbus_valid : OUT std_logic_vector(25 DOWNTO 0);
o_wbus_wdata : OUT std_logic_vector(831 DOWNTO 0);
o_wbus_waddr : OUT std_logic_vector(831 DOWNTO 0);
-- Status and Test Points
o_ro_wbus_debug : OUT std_logic_vector(31 DOWNTO 0);
o_test_points : OUT std_logic_vector(3 DOWNTO 0)
);
end g1_wbus_client_fifos_vhdl;
architecture Behavioral of g1_wbus_client_fifos_vhdl is
Component g1_ipcat_wbus_client_fifo
port(
rst : in std_logic;
wr_clk : in std_logic;
din : in std_logic_vector(51 downto 0);
wr_en : in std_logic;
full : out std_logic;
wr_data_count : out std_logic_vector(9 downto 0);
-- The Client Port is connected to all the read signals
rd_clk : in std_logic;
rd_en : in std_logic;
dout : out std_logic_vector(51 downto 0);
empty : out std_logic;
rd_data_count : out std_logic_vector(9 downto 0);
valid : out std_logic
);
end component;
CONSTANT Almost_Full_Depth : std_logic_vector(9 downto 0) := "0111110100";
type array_26x10 is array(0 to 25) of std_logic_vector(9 downto 0);
type array_26x52 is array(0 to 25) of std_logic_vector(51 downto 0);
SIGNAL almost_full : std_logic_vector(25 DOWNTO 0);
SIGNAL ffdin : std_logic_vector(51 DOWNTO 0);
SIGNAL ff_dout : array_26x52;
SIGNAL ff_write_count : array_26x10;
SIGNAL wbus_count : array_26x10;
SIGNAL wbr_d : std_logic;
SIGNAL upper_adrs_match : std_logic;
SIGNAL wen : std_logic_vector(25 downto 0);
SIGNAL almost_full_d : std_logic_vector(25 downto 0);
SIGNAL wbus_addr_fws : std_logic_vector(25 downto 0);
begin
ffdin <= i_wbus_addr(19 downto 0) & i_wbus_data(31 downto 0);
u_client : for idx in 0 to 25 generate
begin
o_wbus_count(10*idx+9 downto 10*idx) <= wbus_count(idx);
upper_adrs_match <= '1';
--Write only one fifo by decoding 5 address bits.
wbus_addr_fws(idx) <= '1' when (i_wbus_addr(20 downto 16) = i_wbus_fws(5*idx+4 downto 5*idx)) else '0';
wen(idx) <= i_wbus_enable(idx) and i_wbus_wen and upper_adrs_match and wbus_addr_fws(idx);
almost_full_d(idx) <= i_wbus_enable(idx) and '1' when (ff_write_count(idx) > Almost_Full_Depth) else '0';
dc_amf: entity work.dreg_clr_vhdl generic map(1)
port map(
c => i_aur_clk,
ar => i_rst,
e => '1',
d(0) => almost_full_d(idx),
q(0) => almost_full(idx)
);
-- 52 bits x 512, First Word Fall Through.
U_client_ff: g1_ipcat_wbus_client_fifo
port map(
rst => i_rst,
wr_clk => i_aur_clk,
din => ffdin,
wr_en => wen(idx),
full => open,
wr_data_count => ff_write_count(idx),
-- The Client Port is connected to all the read signals
rd_clk => i_wbus_clk(idx),
rd_en => i_wbus_ren(idx),
dout => ff_dout(idx),
empty => o_wbus_empty(idx),
rd_data_count => wbus_count(idx),
valid => o_wbus_valid(idx)
);
o_wbus_waddr(32*idx+31 downto 32*idx) <= "0000000000000" & ff_dout(idx)(50 downto 32);
o_wbus_wdata(32*idx+31 downto 32*idx) <= ff_dout(idx)(31 downto 0);
end generate u_client;
wbr_d <= NOT (OR almost_full);
dc_wbr : entity work.dreg_clr_vhdl generic map(1)
PORT MAP (
c => i_aur_clk,
ar => i_rst,
e => '1',
d(0) => wbr_d,
q(0) => o_wbus_ready);
o_ro_wbus_debug <= X"E" & "00" & almost_full(25 DOWNTO 0);
o_test_points <= x"0";
end Behavioral;