Big Boy
Full Member level 4
I've seen a vew messages on the Net here and there, and I'm having problem with a Spartal-III eval board.
I have an eval board with a Parallel-III interface. The JTAG chain goes like this:
TDI ---> XCF02S ---> XC3S400FG456 --->TDO
When I use the Xilinx iMPACT software (6.2.03i), while I have an design loaded on the FPGA, I can not get reliable communication. IDCODE looping fail under 150 loops. If I hold the FPGA in PROG mode (or if it doesn't have anything loaded), then IDCODE looping work flawlessly.
I tried with a Parallel-IV cable (which I have access to where I work) and in any case, everything is fine all the way...
At first, I taught that it was some noise generated by the FPGA (while runing) which was affecting communications. The Parallel-III circuitry is built onto the board, requiring just a straight cable between PC and the board. However, I tried everything I could (adding de-coupling capacitors, trying different resistors values, ...) and yet, the results stayed the same.
I even took extensive look with a good digital scope and found nothing that could explain the issue (all the signals are clear, no noise, sharp edge, ...).
Looking closely, I found that the config flash (XCF02S) seem to work correctly. It is like if the FPGA just simply doesn't take an instruction (BYPASS or IDCODE depending on which device I IDCODE loop). Then, for example, if I IDCODE loop the flash, then at some point, you see the data (actual ID CODE) coming out of the flash, but not passing through the FPGA. It is as if the TDO output of the FPGA 'Freeze'. Nothing come out of the FPGA at that instent but a bunch of all-ones.
The board also have an header for a 'real' parallel-III cable. I build an equivalent on breadboard and guess what, I get the same failures when accessing JTAG chain while the FPGA is running. IDCODE looping under 100~200 loops.
Looking on the Net, I saw some refferences on people complaining about this mixture of iMPACT/Parallel-III/Spartan.
Does anybody experienced similar problems with a Parallel-III cable and iMPACT?
I have an eval board with a Parallel-III interface. The JTAG chain goes like this:
TDI ---> XCF02S ---> XC3S400FG456 --->TDO
When I use the Xilinx iMPACT software (6.2.03i), while I have an design loaded on the FPGA, I can not get reliable communication. IDCODE looping fail under 150 loops. If I hold the FPGA in PROG mode (or if it doesn't have anything loaded), then IDCODE looping work flawlessly.
I tried with a Parallel-IV cable (which I have access to where I work) and in any case, everything is fine all the way...
At first, I taught that it was some noise generated by the FPGA (while runing) which was affecting communications. The Parallel-III circuitry is built onto the board, requiring just a straight cable between PC and the board. However, I tried everything I could (adding de-coupling capacitors, trying different resistors values, ...) and yet, the results stayed the same.
I even took extensive look with a good digital scope and found nothing that could explain the issue (all the signals are clear, no noise, sharp edge, ...).
Looking closely, I found that the config flash (XCF02S) seem to work correctly. It is like if the FPGA just simply doesn't take an instruction (BYPASS or IDCODE depending on which device I IDCODE loop). Then, for example, if I IDCODE loop the flash, then at some point, you see the data (actual ID CODE) coming out of the flash, but not passing through the FPGA. It is as if the TDO output of the FPGA 'Freeze'. Nothing come out of the FPGA at that instent but a bunch of all-ones.
The board also have an header for a 'real' parallel-III cable. I build an equivalent on breadboard and guess what, I get the same failures when accessing JTAG chain while the FPGA is running. IDCODE looping under 100~200 loops.
Looking on the Net, I saw some refferences on people complaining about this mixture of iMPACT/Parallel-III/Spartan.
Does anybody experienced similar problems with a Parallel-III cable and iMPACT?
