As said above, you have tried to write a computer program that can run step by step on a processor. vhdl is not a programming language. It is a descriptor language. You need to to think about a circuit and then describe it in vhdl. It might look ok as is on the simulator but it won't in a real electronic circuit.
As you people are saying that this is like of software programming I have been working on vhdl since last one month so may be some faults can be there .
I tried to do some changes in my program . I searched on the net and made it with the help of states.Now it is again synthesizing and implement design is also correct . but when i went for test bench wave form it is still not helpful . can you guide me that synthesis report of this program can be useful for me to find out the delay for becoming change signal from 0 to 1 . And there is one doubt also if it cant make any electronics circuit of code then why implement design becomes correct.
This time please give me any solution which i can take .. here is my code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
use ieee.numeric_bit.all ;
entity om is
Port ( clk : in STD_LOGIC; p0 : in std_logic_vector( 2 downto 0 ) ; p1 : in std_logic_vector(2 downto 0 ) ;
reconf : in STD_LOGIC ;reset : in std_logic ; change : out std_logic ; hit : out std_logic ; address : in std_logic_vector(5 downto 0 ));
end om;
architecture Behavioral of om is
type cacheblkpointer is array ( 0 to 7 ) of std_logic_vector( 5 downto 0 ) ;
signal cb : cacheblkpointer ;
type cacheproc is array (0 to 7) of std_logic ;
signal p : cacheproc ;
type set is array( 0 to 3 , 0 to 1) of std_logic_vector( 5 downto 0 ) ;
signal s : set ;
signal discard : std_logic_vector( 5 downto 0 ) ;
type state_type is (s0,s1,s2,s3, s4,s5); --type of state machine.
signal next_s: state_type; --current and next state declaration.
signal pu : integer ;
begin
process( reset , reconf , next_s)
variable f : std_logic_vector( 5 downto 0 );
variable n : integer ;
variable g : std_logic ;
variable l : integer ;
variable h : integer ;
variable k : integer ;
variable c1 : integer ;
variable c2 : integer ;
variable r : std_logic_vector(4 downto 0 ) ;
variable rd : integer ;
variable red : integer ;
begin
if(rising_edge(clk)) then
next_s <= s0 ;
case next_s is
when s0 =>
if ( reset = '1') then
cb(0) <= "010000" ;
cb(1) <= "010001" ;
cb(2) <= "010011" ;
cb(3) <= "010101" ;
cb(4) <= "011001" ;
cb(5) <= "010101" ;
cb(6) <= "010101" ;
cb(7) <= "010101" ;
p <= "01000101" ;
hit <= '0' ;
change <= '0' ;
n := 0 ;
end if ;
next_s <= s1 ;
when s1 =>
if( n < 8 ) then
f:= cb
;
g := p
;
if( g = '0') then
pu <= conv_integer(unsigned(p0)) ;
else
pu <= conv_integer(unsigned(p1)) ;
end if ;
l := conv_integer(unsigned(f)) ;
for i in 1 to 63 loop
h := i-1 ;
k := i ;
c1 := pu * h ;
c2 := pu * k ;
if( c2 = l) then
r := "00000" ;
exit ;
end if ;
if( c2 > l) then
red := l - c1 ;
r := conv_std_logic_vector(red,5) ;
exit ;
end if ;
end loop ;
elsif ( n = 8) then
next_s <= s4 ;
end if ;
next_s <= s2;
when s2 =>
if (g = '0') then
rd := conv_integer(unsigned(r)) ;
else
rd := conv_integer(unsigned(r)) + pu ;
end if ;
next_s <= s3;
when s3 =>
if( rd > 0 and rd < 4) then
if(s(rd,0) = "000000") then
s(rd,0) <= "010000" ;
else
if(s(rd,1) = "000000") then
s(rd,1) <= "010000" ;
else
discard <= "010000" ;
end if ;
end if ;
else
discard <= "010000" ;
end if ;
n := n + 1 ;
next_s <= s1;
when s4 =>
change <= '1' ;
next_s <= s5 ;
when s5 =>
for i in 0 to 3 loop
for j in 0 to 1 loop
if(s(i,j) = address) then
hit <= '1' ;
else
hit <= '0' ;
end if ;
end loop ;
end loop ;
end case ;
end if ;
end process ;
end Behavioral;