I have a design, named aaa which consists of ram generated using Core Generator. The ram design generated consists only io ports.
So, i take this design aaa into Xilinx ISE ver 5.1. When i read it at Translate Level, it fails, giving error message saying that it couldn't resolve the module for ram.
How should i read in my files? How does Xilinx ISE5.1 looks for the ram design? It doesn't seemed to be reading it.
My experience is that when you generate a core using CoreGen in all case you have to generate the core with some standard pins like ND, CE, RDY.
In fact if you don't , first you will have problem to simulate the core, and second if you don't need this ports you just left them open in your top_design.vhd