Problem of Resistor matching

[hacksgen]

HI friends,

a question on resistor matching. I am using the umc 130nm technology. As per the documents given the resistors can have a mismatch of upto ±10% betweent he actual value in the circuit and after fabrication. In my circuit i am using two resistors of same value and the value difference between them after fabrication shoudl be really low. taking the worst case as per umc process documents the tolereance they hae specified will give a large error assuming their is +10% error in the first resistor and -10% error in secodn resistor. Is their any way of balancing this mismatch during fabrication of the resistors.

Thanks for your help.

 

[renwl]

the two resistor should be matched when layout

 

[hacksgen]

I know that . But with the common centroid and interdigitization layout techniques, by how much can the mismatch be reduced.

Added after 56 seconds:

I need mismatch of less than .1% between the two resistors. Can that be achieved using the common centroid and interdigitization layout technique

 

[rfsystem]

There is a resistor mismatch within a small area between two technological equal resistors.

And there is an technological spread.

Because of the value it seems to be a spread. Search for geometric dependent mismatch in your doc.