[SOLVED] problem moving from SLL to shift_left in ISE 14.5

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
library UNISIM; 
use UNISIM.vcomponents.all;

entity g1_applic_top_vhdl is
  GENERIC (           
    Hotlink_SDMA_Base     : integer := 0; -- Define the first SDMA engine used by HOTLINK instance 0.
    used_engine_mask      : std_logic_vector(31 downto 0) := (X"0000FFFF" SLL Hotlink_SDMA_Base) OR '0'; -- Set 16 bits = 8 Hotlink ports * 2 engines
    used_wbus_chan_mask   : std_logic_vector(25 downto 0) := ("00000000001111111111111111" SLL Hotlink_SDMA_Base) OR '0' -- Set 8 bits = 4 Hotlink ports * 2 wbus_chans	                
  );	
  PORT ();

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
library UNISIM; 
use UNISIM.vcomponents.all;

entity g1_applic_top_vhdl is
  GENERIC (           
    Hotlink_SDMA_Base     : integer := 0; -- Define the first SDMA engine used by HOTLINK instance 0.
    used_engine_mask      : std_logic_vector(31 downto 0):= shift_left(X"0000FFFF", Hotlink_SDMA_Base) OR '0'; -- Set 16 bits = 8 Hotlink ports * 2 engines
    used_wbus_chan_mask   : std_logic_vector(25 downto 0):= shift_left("00000000001111111111111111", Hotlink_SDMA_Base) OR '0' -- Set 16 bits = 8 Hotlink ports * 2 wbus_chans	                
  );	
  PORT ();

Architecture behavioral of Entity g1_asa_top_vhdl is up to date.
Compiling vhdl file "C:/ProgramData/Teradyne/FPGA/ISEProjects/App0x3120VHDLMaster/src/g1_applic_top_vhdl.vhd" in Library work.
ERROR:HDLParsers:808 - "C:/ProgramData/Teradyne/FPGA/ISEProjects/App0x3120VHDLMaster/src/g1_applic_top_vhdl.vhd" Line 44. OR can not have such operands in this context.
ERROR:HDLParsers:808 - "C:/ProgramData/Teradyne/FPGA/ISEProjects/App0x3120VHDLMaster/src/g1_applic_top_vhdl.vhd" Line 45. OR can not have such operands in this context.
Entity <g1_applic_top_vhdl> (Architecture <behavioral>) compiled.
--> 

Total memory usage is 4566752 kilobytes

Number of errors   :    2 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)


Process "Synthesize - XST" failed

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
library UNISIM; 
use UNISIM.vcomponents.all;

entity g1_applic_top_vhdl is
  GENERIC (           
    Hotlink_SDMA_Base     : integer := 0; -- Define the first SDMA engine used by HOTLINK instance 0.
    used_engine_mask      : std_logic_vector(31 downto 0) := X"0000FFFF" ; -- Set 16 bits = 8 Hotlink ports * 2 engines
    used_wbus_chan_mask   : std_logic_vector(25 downto 0) := "00000000001111111111111111"  -- Set 8 bits = 4 Hotlink ports * 2 wbus_chans	                
  );	
  PORT ();