Problem in Xilinx core generator (FIFO)

[syedahmar]

xilinx core generator

Hi all!!
I am currently working on a project and i am facing a problem which i hope someone in here would solve.
In my project there are four 32 bit,1024 depth FIFO. Now the problem is of making it come in a single device. When i generate this FIFO from the core generator and then after synthesis, sometimes it sysnthesise the RAM blocks as four input BRAM and sometimes as 16 input Ram blocks. And i do not change any settings. There is no problem of area if it uses 16 BRAM blocks but with 4,it cant work. I want to know, is there any way i can make Xilinx ISE to use 16 input BRAM units.
Help plzzzzzz....

 

[Big Boy]

xilinx fifo example

Depending on the device, BRAM have either 4K or 16K (plus some bits for parity).

So, if you have a device which have only 4K BRAM (Spartan-2, Virtex, and lower), if you define fifo depth of 1024, this leave only 4-bits wide data path.

Spartan-III, Virtex-II, and higher have 16K (18K with the parity bits) BRAM. Still, this leave a max of 16x1024 bits RAM.

To have 32x1024 BRAM, you'll have to use multiple BRAM in parallel. I don't know if the core generator can do this by default.

Also remember that BRAM resources are limited. In a 4K BRAM device, 4 32x1024 FIFO will consume 32 BRAM. In a 16K (18K) BRAM device, it will consume 8 BRAM.

 

[ilikebbs]

xilinx fifo problem

Coregen will automatically use multiple BRAM to realize your fifo size.
For example: BRAM size is 4K in Spartan-II device.
If you define a fifo with 32bit width,1024 depth.
Coregen will use 8 BRAM to realize your fifo If your device has enough BRAM.

 

[syedahmar]

xilinx coregenerator fifo

But my problem was that the core generator does use 16 BRAM cells ..but not all the time....sometimes when i generate, it uses 4 bit BRAM and sometimes 16 bit....and i do not change any settings......what to do??

 

[shakeebh]

xilinx fifo problems

well u can try looking into the manuals of constraint editor to see how its done.

PS: If u dont know what is a constraint editor, at times when for ny reason we arent comfirtable with the device configuration being done by XST (Xilinx's synthesizer), we define constraints to restrict it to a particular configuration out of many possible to implement that logic.

Added after 4 minutes:

u can see the constraint editor guide at :

https://www.xilinx.com/support/sw_manuals/xilinx7/download/ for ISE 7

**broken link removed** for ISE 6

 

[echo47]

fifo core generator

What version ISE and Coregen are you using? Maybe it has a bug. I've seen Coregen forget one or two GUI settings between runs, or sometimes a checkbox doesn't stick properly. When I want to change something in my generated core, I usually delete the old core files and then regenerate the core from scratch.

 

[syedahmar]

download xilinx fifo generator

Thanks!!!!
i deletd my old core and regenerated a new one and the problem has been solved
...
Thanks alot to all of you....

 

[power-twq]

generating fifo without using brams

you can use dualport ram and add some logic to generate your own fifo,

this canbe safe to use xilinx's fifo directly.

Hi all!!
I am currently working on a project and i am facing a problem which i hope someone in here would solve.
In my project there are four 32 bit,1024 depth FIFO. Now the problem is of making it come in a single device. When i generate this FIFO from the core generator and then after synthesis, sometimes it sysnthesise the RAM blocks as four input BRAM and sometimes as 16 input Ram blocks. And i do not change any settings. There is no problem of area if it uses 16 BRAM blocks but with 4,it cant work. I want to know, is there any way i can make Xilinx ISE to use 16 input BRAM units.
Help plzzzzzz....