problem in verilog netlist please try to slove it.

[kirteshmiet]

hi in my verilog netlist which has come after synthesis . there is one IO pad instentiate in it . so for this IO pad there are two pins one is PAD and other is C . PAD pin is connected to port and C pin is connected to a net in the design. so how to make connection between PAD and C pin as the signal comming from port has to go in the design through C pin as it is a clock signal.

PISN U_Clk60 (
.C(\U_sBoxRam/udpRam256x8_bist_con/dpRam256x8_bist_dpRam256x8_block_0_instance_0/dpRam256x8_bypass_0_instance_0/bp_clk_12 ),
.PAD(Clk60));

her Clk60 is the port connected to PAD , C is connectd to a net ,PISN is the lef module name taken from IO lef and U_Clk60 is the instance name in the verilog netlist so thell me how to make a connection between C and PAD pins of IO PAD.

thanks
kitty...:-D

 

[rca]

I don't understand your problem.
The connection is made inside the component PISN which you should apace a model in Verilog r VHDL to represent the behavioral model?

 

[kirteshmiet]

I don't understand your problem.
The connection is made inside the component PISN which you should apace a model in Verilog r VHDL to represent the behavioral model?

Hi rca ,

I got the solution if you give timing lib for that then it will make a connection in between them.

Thanks for your reply..