hamidyadegaramin
Newbie level 4
I am designing a noise shaping block as seen here the Simulink file is also attached. I accomplished it in Simulink and want to transfer it to Verilog. However, I faced with very robust miscalculations. The output in Verilog goes unstable . I have no idea how to solve it. If possible could you please your comments and idea about the design?
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 module MSBx (clk, rst, I,FB1,FB2,O,O2); input signed[13:0] I; input signed[13:0] FB1; input signed[14:0] FB2; output signed [14:0] O; output signed [14:0] O2; input rst; input clk; wire signed [13:0] FB1; wire signed [14:0] FB1_; wire signed [14:0] FB2_; wire signed [17:0] I2; wire signed [14:0] FB2; wire signed [14:0] RFB2; wire signed [14:0] RFB1; wire signed [17:0] OINT1; wire signed [17:0] OINT2 ; wire signed [17:0] Iinteg_1; wire signed [17:0] Iinteg_2; wire signed [14:0] SQO; wire signed [17:0] SQE; wire signed [14:0] SQI; //assign RFB1= {OINT2[14:10],10'b0000000000}; //assign RFB2= {OINT2[14],OINT2[14:1]}; assign I2 [17:0]= {{4{I[13]}},I[13:0]}; //assign FB1_ [14:0]= {FB1[13:0],1'b0}; //assign FB2_ [14:0]= {FB2[13],FB2[13:0]}; assign Iinteg_1 = I2-SQOE+OINT1; assign SQI = OINT2[14:0]; assign SQOE={{3{SQO[14]}},SQO[14:0]}; assign Iinteg_2=OINT1+OINT2-SQOE<<<1; assign O=SQO[14:0]; assign O2=OINT1[14:0]; INT integ1x(.clk(clk), .rst(rst), .I(Iinteg_1), .O(OINT1)); INT integ2x(.clk(clk), .rst(rst), .I(Iinteg_2), .O(OINT2)); SQ SQx(.clk(clk), .rst(rst), .I(SQI), .O(SQO)); endmodule /////////////////////////////////////////// module INT (clk,rst,I,O); input clk; input rst; input [17:0] I; output reg signed[17:0] O=0;; always@(posedge clk) begin O <= I ; end endmodule //////////////////////////////////////// module SQ (clk,rst,I,O); input clk; input rst; input signed [14:0] I; output reg signed[14:0] O=0; always@(posedge clk) begin if (O > 15'b010000000000000) begin O <= 15'b010000000000000; end if(O < 15'b110000000000000) begin O<= 15'b110000000000000; end if (15'b110000000000000< O < 15'b010000000000000) begin O[14:10] <= I [14:10] ; O[9:0] <= 10'b0000000000; end end endmodule
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