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Problem in using PLL - need 108Mhz signal to clock EPM7064S

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Rameez Ahmad

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Hi,I am using this chip Cdcs502 from Ti.I am running a 27Mhz crystal and connecting Capacitor load of 35pF ,with FS=0,the output is a clock pulse with 0.8 low and 2.1 high,i think this is fine.But the problem is when i do FS=1,the frequency gets 108Mhz but the amplitude becomes very low , the peak to peak amplitube is 800mV having a DC offset of 1.6 V...Kindly help me with this..]

I need this 108Mhz signal to clock my EPM7064S.

Kindly help!!
 

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