[SOLVED] Problem in using generate statement in verilog

[vishi]

I want to use the for loop inside generate statement to be infinite as shown below. But the problem is I cannot stop or quit the loop at some condition using "disable text". neither i am able to use keyword "break".
It is showing an error:

unexpected token: 'disable'
unexpected token: ';'

please help me by solving this or suggest an alternative. thanks

My verilog code is:

---

Code Verilog - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
module top(a1,a3,wj,d4,d10,d2,dc,dtot);
input [11:0]a1,a3,wj;
input [3:0]d4;
input [9:0]d10;
input [1:0]d2;
input [25:0]dc;
output reg[25:0]dtot;
 
reg [11:0]alpha1,alpha3;
reg [25:0]dt,error;
 
            genvar i;
            generate
            for (i=1;i>0;i=i+1-1)begin:test
 
                assign a1[11:0]=alpha1[11:0];
                assign a3[11:0]=alpha3[11:0];
 
                calb_top t1(a1,a3,wj,d4,d10,d2,dc,dt,error,alpha1,alpha3);
                
                if(error==26'b00000000000000000000000000)begin
                disable test;
                //break;
                end
            end
            endgenerate         
        assign dtot=dt;
  endmodule

---

 

[ads-ee]

Learn what a for loop is used for in HDL, it's not for iterating through time (like in software) it's for replicating stuff.

I'm assuming you are trying to write testbench code as what you are proposing is very software like. Add a loop with a time control statement (use google to learn about that).

something like this would do the software thing you are attempting.

---

Code Verilog - [expand]
1
2
3
4
5
6
7
8
9
10
11
reg enable_loop;
initial begin
  enable_loop = 1;
  while (enable_loop) begin
    if (error == 26'b0) begin
      enable_loop = 0;  // exits loop
    end
  end
  #100; // delay 100 timeunits and check again.
end
calb_top uut(/*your ports*/);

---

 

[vishi]

I tried this, but the problem is ...this would instantiate the module calb_top only once.
But i want to keep instantiating it until the error becomes zero. (Error is one of the output port from the module calb_top.)
So, if i instantiate it within while loop, it would require generate statement (as instantiation is structural). Thats why i was using generate statement.
And "generate while" does not exist so i used "generate for".
Further this generate statement could not be used in initial-begin block.
So, the problem is i am not able to exit this for loop by neither of the three options:- using disable, using break, or updating variable i to 0. All of them give error.

 

[ads-ee]

instantiating a module isn't like "calling" a subroutine in a programming language.

I think you need to read a book on VHDL that TARGETS hardware design. You obviously don't understand what VHDL code is supposed to be used for.

It is impossible to make hardware that self modifies the design based on outputs of the design itself. All the hardware has to exist from the start. Hence all loops have to be unrolled and absolutely must have constants for the range of indices.

If someone could come up with silicon that does this they would soon become the richest person on the planet.

 

[vishi]

@ads-ee thanks.. I understood your point :grin: