Problem in using bsim SOI veriloga code in Cadence

[Sitansusekhar]

Hi,
I was trying to simulate verilog-A code of bism SOI v4.4 (Code is taken from berkely site). When I am using that in hspice it work perfectly without any problem. But when I tried to generate cell view in cadence using this code I am getting syntax error for $param_given, ddx etc. can ypu plz help me?

 

[dick_freebird]

Not seeing the errors, I imagine this may be you needing
to edit the CDFs in order to pass the expected params to
the netlist line.

 

[Sitansusekhar]

Hi dick_freebird,
Thanks for reply. I can edit CDF once I created cellview. But I am not able to create cell view. when I am trying to create cellview it shows syntax error in verilog code. Can u plz helpme ???

 

[Theodora Rezk]

Hi Sitansusekhar

if u want to use the bsimsoi models, u don't need to generate a cell view for it in cadence
as cadence already had included this model in analogLib library
the name of the cell view is: nsoip (for nmos) and psoip (for pmos)
but you need a model card to make the simulation.

is that what u need?

 

[dick_freebird]

Hi dick_freebird,
Thanks for reply. I can edit CDF once I created cellview. But I am not able to create cell view. when I am trying to create cellview it shows syntax error in verilog code. Can u plz helpme ???

Yes, the Cadence-spawned veriloga editor will automatically
check syntax and you may have to save-as to save, at all,
if you don't fix the errors. So fix the errors. What those are,
I do not know, and I'm not real good at coding myself. Usually
I just rip off some existing example and change as little as
possible.

There should however be an error report, follow it to the first
error and fix it, repeat until done.

You should start with a symbol cellview (I'd copy the analogLib
NMOS if you have nothing better). Once you have -any- cell
view the CDF can be edited.

 

[Bagherieda]

Hi Sitansusekhar,

I'm having the same issue. Have you found the solution yet?

Cheers,