Problem in simulation - difference between SPICE simulation

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fasto2008

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Problem in simulation

Hello everybody,

Is there big difference between SPICE simulation design layout and simulation same electrical circuit.
Because i find in my simple current mirror with two NMOS bandwidth =13.6KHZ.
And when i design layout with L-EDIT TANNER and after extracting file spice i find bandwidth=532 HZ .
Please help me

Thank you in advance
 

Problem in simulation

That would mean your current is 1nA or less, and the layout routing adds 20-fold capacitances to the inherent transistor capacitances. Check your extracted netlist for such big parasitics!
Cheers, erikl
 

Re: Problem in simulation

Thank you erikl for your help but the problem isn't with current because i simulate less than 1 nA and more , i have the same problem.
I check again my extracted netlist for parastic capacitances and until now i have the same problem.
Please help me.
 

Problem in simulation

In this case I'd suggest to remove (out-comment) the parasitics in your extracted netlist (maybe one-by-one, and all of them in the end) and find out which parasitic cap(s) (or inductance(s)?) is/are responsible for destroying the bandwidth.
You are sure you use the same transistor models in both your pre- and postLayout netlists?

Good luck! erikl
 

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