problem in rtl simulation

[sdmotewar]

hello everyone
i m doing pipelined mac unit in dsp processor as a rtl model
it is pipelined by adding register in between stages
indivisual blocks of multiply, accumulation, registers all gives correct simulation output
but overall simulation of rtl gives correct output upto product, but does not give correct output of accumulation since it uses feedback of accumulating previous stage o/p
i m using ise9.2 simulator

 

[asic_guru]

If I understand right, when you tested out the individual blocks, they produced the desired results. However on connecting them all together you do not see the desired overall output, is that right?
The whole is always greater than the sum of its parts ! Did you check the connections ? Can you tap into the signals of the interface between the penultimate stage and the last stage ?

 

[sdmotewar]

thank u
i got results now

 

[sdmotewar]

Re: problem in rtl simulation of dsp processor

hello all
i m doing vhdl simulation for dsp procesesor core, for load operation, data from data memory is available at input of temp register ( which is multiple output register), but at output data is not transfered even thougth all necessary enable signals are activated.
what could be problem???