How to connect reset pin to all flip-flops in gate level netlist that is generated after synthesis through Design-Compiler(synopsys tool).
{as like clock, reset pin must be connected to each flipflops to reset output} .
(NOTE: undefined states of flips are creating problem during post synthesis simulation to get right results.)
I assume that it is not using a cell with an unconnected reset input port.
The problem with synchronous resets is that you can and will create logic that is correct in silicon but cannot be simulated. by verilog. The solution is to have separate synchronous and asynchronous resets on every flip flop and use the async reset only during simulations.
Once a flop has a known value then the synchronous reset will work.
Do not connect the async reset to your boards power on reset signal. Connect it to the same simulation reset that you use for your clock dividers.
How to connect reset pin to all flip-flops in gate level netlist that is generated after synthesis through Design-Compiler(synopsys tool).
{as like clock, reset pin must be connected to each flipflops to reset output} .
(NOTE: undefined states of flips are creating problem during post synthesis simulation to get right results.)
How to connect reset pin to all flip-flops in gate level netlist that is generated after synthesis through Design-Compiler(synopsys tool).
{as like clock, reset pin must be connected to each flipflops to reset output} .
(NOTE: undefined states of flips are creating problem during post synthesis simulation to get right results.)
I modified netlist replacing all flop-flops with other types of flip-flops which have reset pin then connected all reset pins to my design RESET pin.
after that gate level simulation matched with behavior simulation results.
Is it right way?
is it right to modifying the gate-level -netlist ?
NOTE:
(This become easy by using short key "Ctrl +h" find and replace )
(VCS is used for simulation)
I modified netlist replacing all flop-flops with other types of flip-flops which have reset pin then connected all reset pins to my design RESET pin.
after that gate level simulation matched with behavior simulation results.
Is it right way?
is it right to modifying the gate-level -netlist ?
NOTE:
(This become easy by using short key "Ctrl +h" find and replace )
(VCS is used for simulation)
I modified netlist replacing all flop-flops with other types of flip-flops which have reset pin then connected all reset pins to my design RESET pin.
after that gate level simulation matched with behavior simulation results.
Is it right way?
is it right to modifying the gate-level -netlist ?
NOTE:
(This become easy by using short key "Ctrl +h" find and replace )
(VCS is used for simulation)
You NEVER modify a gates level netlist. You either fix the input or the tool so that it produces the correct output. Modifying a netlist is a HACK and doing it is likely going to come back and haunt you in the future.
You NEVER modify a gates level netlist. You either fix the input or the tool so that it produces the correct output. Modifying a netlist is a HACK and doing it is likely going to come back and haunt you in the future.
thanks for advice
I am going to modify my verilog code using "asynchronous RESET " in a way that it will connect RESET pin to all flipflops as like a clock in gate-level-netlist .
thanks for advice
I am going to modify my verilog code using "asynchronous RESET " in a way that it will connect RESET pin to all flipflops as like a clock in gate-level-netlist .
Did you read my first reply where I told you NOT to do that?
Do not touch your current code. Add an additional async reset to all flops and connect that to your simulation reset. You will need two separate reset systems. An async one that is never driven
except by your simulator and a synchronous one driven by your power on reset signal.