Problem in opamp design as W and L may alter a bit

[xibeizi]

I designed an opamp. but I found that a little alter of W and L could make large alter to the gain. if there is 0.1um change with W or L , the gain will change with 10dB to 20dB. is that feasible? how should I avoid this problem?

 

[gpwu]

Re: the op problem

Only possible in deep sub micron design.
You can check you DC bias point and make sure it's reasonable before running ac anlaysis. Maybe some devices is in the triode region.

 

[xibeizi]

the op problem

My process is 0.5um.is it deep sub micro process?

 

[solidstate]

the op problem

Please post your schematic. If you have a differential high impedance node, is your CMFB working allright?

 

[xibeizi]

the op problem

what is useness of high impedance node ?

 

[gpwu]

Re: the op problem

No, it is not deep sub micron process.
I also used around 0.5u process, and noticed L lateral diffusion is quite significant.
You can prove this by simulating two long channel device, L>3u, and see the current mismatch. Bet you it will be real close matched.

 

[kumar123]

Re: the op problem

I designed an opamp. but I found that a little alter of W and L could make large alter to the gain. if there is 0.1um change with W or L , the gain will change with 10dB to 20dB. is that feasible? how should I avoid this problem?

Hi is this current mirror load opamp? then how do u find the small-signal gain Av ?
which type of simulation tool do you use

Regards
Kumar123

 

[nan_ishan]

the op problem

possible in deep sub micron design...
which tool are u using....Microwind?

 

[xibeizi]

the op problem

I use Hspice to simulate op. it is current mirror load op. when I change the bias circuit pmos size of 0.1um. the gain alter 10dB.

 

[huojinsi]

Re: the op problem

I feel your DC operation point is somewhat problem, pls post the schematic of op and plot the open loop ac response curve of the op!

 

[yschuang]

Re: the op problem

What region does your pmos mirror operate ? Make sure your Vgs-Vt> 2nVt=78mV
, like 200mV, and then your pmos mirror will in saturation.

 

[jerryzhao]

the op problem

Dfferential output or singal output? If you say current mirror load, I think it is singal output, but you only alter one loading PMOS or two or the bias(which bias?)? Could you up load your cirucit, or describe it detail.

 

[safwatonline]

the op problem

check ur common mode feedback