anilineda
Member level 3
I have a Dual port RAM design with ports like
i created an axi slave peripheral in vivado and inlcuded above .v file, now the question is, how to instantiate this code with the standard axi4 interface signals, i tried like this below without using any user port declarations separately .
but im getting multidriven error with S_AXI_RDATA signal while optimizing the design. please correct me, if i am going wrong totally. otherwise rewrite those 6 lines for me, plz.
Code:
input clk,
input [31:0] mem_awaddr,
input [31:0] mem_araddr,
input [7:0] mem_wdata,
output [7:0] mem_rdata,
input write_en
i created an axi slave peripheral in vivado and inlcuded above .v file, now the question is, how to instantiate this code with the standard axi4 interface signals, i tried like this below without using any user port declarations separately .
Code:
dpram inst (
.clk(s_axi_clk),
.mem_awaddr(S_AXI_AWADDR),
.mem_araddr(S_AXI_ARADDR),
.mem_wdata(S_AXI_WDATA),
.mem_rdata(S_AXI_RDATA),
.write_en(S_AXI_AWVALID)
)
but im getting multidriven error with S_AXI_RDATA signal while optimizing the design. please correct me, if i am going wrong totally. otherwise rewrite those 6 lines for me, plz.
Last edited: