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HI there,
I have a HLS generated IP core , which I want to connect to Axi- DMA with MicroBlaze processor. I get the following error.
Can someone guide me here?
Hi there,
Thanks for reply..
M_AXIS_MM2S and OUTPUT_STREAM have 200Hz and 100Hz respectively. But i am not able to change the frequency for M_AXIS_MM2S because it is fixed.
what can i do? How do i change the frequencies between blocks?
It would be easier for someone to look at the design if you wrote out the BD Tcl script so someone else can look at the design.
From the limited view you have in your pictures. It looks to me like you have two different clocks running the master and slave sides of everything. If they are different frequencies I'm pretty sure you need to use clock crossing blocks in the design to transfer between the clock domains.
HI ,
Thanks for reply..
I dont use Tcl scipt, I use GUI directly. Here is my complete design in IP Integrator..
Can you please tell me where i am going wrong?
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