I am trying to find the response of a set of cascaded inverters into a pass-transistor. First, I put "one" inverter (configured of an NMOS & PMOS) and connected it into the pass-transistor. The response was significantly and the transistors in inverter were in regions 0 Tcut-off) or 1 (triode). Second, I put "two" inverters connected into the pass-transistor and I found that the pass-transistor went into region 3 (saturate) and the regions of first inverter were 2 for PMOS and 1 for NMOS and 0 & 1 for the second inverter ...!!
Anybody could help me to understand this phenimenon?
The output of the pass transistor is not a Rail to Rail output (i.e 0 to 1.8V).....
the pass transistor can only pass Vgs-Vth voltage on the output.....
This Vgs-Vth drop causes the pass transistor to remain in saturation region.... (1 st result)
this Vgs-Vth reduction in the output voltage level causes the first inverter after the pass gate's pmos/nmos to be in saturation and cut-off .......
After the inverter output, the signal again gets its full amplitude level ... so the last inverter's pmos/nmos will be triode and cut-off.... and the output is same as input with some logic delay......
Hope this is correct... and any doubts let me know...