problem in a pipeline ADC

[omarkhan84]

HI I am working on a 4 bit pipelined ADC . I am using two 1.5 bit stages and one 2 bit stage with a flash ADC . The two 1.5 bit stages include sub-ADC , sub-DAC and MDAC . I am using one SHA at the input . I ran different simulation . First I tested the 1.5 bit stage independently . With real blocks and its working . Then I simulated the 4 bit system . But this time I am using a real SHA abut all the otehr blocks are ideal . Problem is I am not getting a correct output from the SHA . Can anyone help me out with this issue . ?

 

[xiahanzh]

So you know it is the problem of SHA, but you do not give any schematic or simulation results, how can I know what the issue is.