megaknaller
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Hi,
I´m designing a 110 GHz CE amplifier and since I´m quite new in the hands-on IC design I am running already into trouble when understanding how the bias of the whole amplifier is performed. Attached there´s an image of a typical LNA architecture.
In this example, how is the biasing of the first cascode stage performed? Assumming that L_D1, L_D2, the interstage coupling capacitor as well as the parasitic transmission lines (interconnection) work as the interstage impedance matching between stage 1 and 2, how is it exactly that the biasing here works? I mean, if i understand this correctly, L_D1 and L_D2 act as short circuit on DC, which sets the collector voltage of the cascode transistor to VCC and therefore, this voltage cannot "swing" more than the fixed Vcc, which would mean that the amplified AC signal could not fully develop into it?
For the sake of clarity, if say, for example, there would be a resistor between Vcc and the cascode transistor's collector, at DC the collector voltage V_c would be lower than V_cc, therefore, the amplified AC voltage signal could swing on top of the DC level and eventually reach the VCC value, where it would clip and occassionate some distortion.
I know I´m missing some important, maybe very basic, understanding point here how this thing works and would be very grateful if someone could provide me with some explanation or literature about this.
Many thanks in advance.
I´m designing a 110 GHz CE amplifier and since I´m quite new in the hands-on IC design I am running already into trouble when understanding how the bias of the whole amplifier is performed. Attached there´s an image of a typical LNA architecture.
In this example, how is the biasing of the first cascode stage performed? Assumming that L_D1, L_D2, the interstage coupling capacitor as well as the parasitic transmission lines (interconnection) work as the interstage impedance matching between stage 1 and 2, how is it exactly that the biasing here works? I mean, if i understand this correctly, L_D1 and L_D2 act as short circuit on DC, which sets the collector voltage of the cascode transistor to VCC and therefore, this voltage cannot "swing" more than the fixed Vcc, which would mean that the amplified AC signal could not fully develop into it?
For the sake of clarity, if say, for example, there would be a resistor between Vcc and the cascode transistor's collector, at DC the collector voltage V_c would be lower than V_cc, therefore, the amplified AC voltage signal could swing on top of the DC level and eventually reach the VCC value, where it would clip and occassionate some distortion.
I know I´m missing some important, maybe very basic, understanding point here how this thing works and would be very grateful if someone could provide me with some explanation or literature about this.
Many thanks in advance.
