Problem adding reset to master slave D-FF for phase detector

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Hello, I have built a UMC90nm master slave D flip flop which is working fine.
Next i tried to implement a RESET functionality to the D-FF which also worked fine
as shown in the photo bellow,however when i connect in the configuration as shown in the schematics bellow, something when wrong.
I think its because that we the RESET signal generated from the outputs of the FLIP FLOPS
so in some manner it resets its self.
where did i go wrong?
Thanks


 

however when i connect in the configuration as shown in the schematics below, something when wrong
Click to expand...
What did you observe?
 

FvM said:
What did you observe?
Click to expand...
Hello ,For phase detector We input in both flipflops VDD and the out puts turns zero when reset is VDD.
i am reseting using connecting directly to VDD or GND depending on what node it sits.
to produce the reset signal i am DOINg Q AND Q2 as shown bellow.
however something in that reset process goes wrong.
when i am doing externa singnal reset FLIP FLOP RESETS FINE, but in this AND configuration which is very trivial some this make it go wrong.
where did i go wrong?
Thanks.


 

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I don't understand what you consider "wrong" in the posted simulation waveforms. I don't recognize missing pulses or similar artefacts. Please clarify where exactly you see a problem.

I presume that an asynchronous circuit like this has some timing requirements, e.g. a certain path delay for the reset signal to guarantee a sufficient reset pulse width. Otherwise one of both channels might miss the reset. These prerequisites are not necessarily discussed in the literature suggesting the phase detector. As far as I remember e.g. Razavi only shows a circuit without further comments.

- - - Updated - - -

In addition, there's a circuit discussion in Razavi, Design of Integrated Circuits for Optical Communications, paragraph 8.2.2 Phase/Frequency Detector and Charge Pump. Similarly in Razavi, RF Microelectronics.
 

Hello, i am trying to focus on the first reset pass gate sector.
we have data of VDD when CLK2 is ON or OFF we pass VDD(after_tg12 net) threw the pass gate,only when reset=VDD after_tg12 net should go to zero but instead after_tg12 net goes to zero when clk2=VDD
although CLK2 only open and closes the pass gate,it cannot set after_tg12 net to zero.
Where did i go wrong?
Thanks




 

In a regular master slave FF, the asynchronous reset signal is expected to immediately reset both stages independent of the clock state, that's what we apparently see in your waveforms, although they are hard to read (all traces merged on the same axis).

See below a DFF macro from an ASIC library.



Apart from the latest simulation, I don't understand where you see a wrong behavior of the phase detector circuit in the post #3 waveforms.
 

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