Problem about 9k block ram in Spartan 6

[NaneBL]

Hi friend. I am programming a slave modbus device into a Spartan 6 and I get this warning in map implement:

WARNINGhysDesignRules:2410 - This design is using one or more 9K Block RAMs
(RAMB8BWER). 9K Block RAM initialization data, both user defined and
default, may be incorrect and should not be used. For more information,
please reference Xilinx Answer Record 39999.

I have looked for about it, and I have found some solutions, but I do not understand well.

**broken link removed**

I use ISE 13.1. Do you know how select 18k block ram in ISE Design for implemention?

I think this is the code which use my 9k block ram.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

Entity fifo is
	Port (  CLK           : in std_logic;
		  RESET	 : in std_logic;
		  RD		 : in std_logic;
		  WR		 : in std_logic;
		  W_DATA    : in std_logic_vector(7 downto 0);
     		  EMPTY	 : out std_logic;
		  FULL         : out std_logic;
		  R_DATA     : out std_logic_vector(7 downto 0));	   
END fifo;-- entity declarations ends

Architecture A_fifo of fifo is
	Type Mem is array (255 downto 0) of std_logic_vector( 7 downto 0);
	Signal Memory : Mem;

	Signal ReadPointer   : std_logic_vector(7 downto 0);
	Signal WritePointer  : std_logic_vector(7 downto 0);
	Signal ByteCounter   : std_logic_vector(8 downto 0);
	Signal WriteEnable   : std_logic;
	Signal ReadEnable    : std_logic;
	Signal FifoFull      : std_logic;
	Signal FifoEmpty     : std_logic;

Begin
	----------------
	-- Ram memory --
	----------------
	Write_Process : Process(clk)
	Begin
		if (clk'event and clk = '1') then
			if ( WriteEnable = '1') then
				Memory(Conv_Integer(WritePointer)) <= w_data;
			end if;
			if ( ReadEnable = '1' ) then
				r_data <= Memory(Conv_Integer(ReadPointer));
			end if;
		end if;
	end process; 

	--r_data <= Memory(Conv_Integer(ReadPointer));

    ----------------------
	-- Pointers control --
	----------------------
	ReadWriteFifoOut   : Process(Clk,Reset)
	Begin
		IF ( Reset = '1') then
			ReadPointer  <= "00000000";
			WritePointer <= "00000000";
			ByteCounter  <= "000000000";
		ELSIF(Clk'event and Clk = '1') then
			IF ( WriteEnable = '1' and ReadEnable = '0') then
				WritePointer <= WritePointer + 1;
				ByteCounter  <= ByteCounter + 1;
			END IF;
			IF ( ReadEnable = '1' and WriteEnable = '0') then
				ReadPointer  <= ReadPointer + 1;
				ByteCounter  <= ByteCounter - 1;
			END IF;
			IF ( ReadEnable = '1' and WriteEnable = '1' ) then
				WritePointer <= WritePointer + 1;
				ReadPointer  <= ReadPointer + 1;
			END IF;			
		END IF;
	END process;
	
	-------------------------
	-- Combinatorial Logic --
	-------------------------
	FifoEmpty <= '1' when ( ByteCounter = "000000000") else '0';
	FifoFull  <= ByteCounter(8);
	Full  <= FifoFull;
	Empty <= FifoEmpty;
	WriteEnable <= '1' when ( Wr = '1' and FifoFull = '0') else '0';
	ReadEnable <= '1' when ( Rd = '1' and FifoEmpty = '0' ) else '0';

	
END A_fifo;--Architecture Ends

 

[NaneBL]

I have detected an error during testing, but I am not sure if it is a design error or an error due to the last warning.

The simulation with ModelSim is correct, but when I test in Nexys 3 board, when I am filling up the FIFO, I can't write in the register "Memory(7)", it writes again in Memory(0).

Can you give me any idea? Thanks.

EDIT: I have checked when value of WritePointer must to increment from 6 to 7, it does it from 6 to 0, but I do not know why.