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Probelm with clock network latency

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Mariammm

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Hi,
I have a setup violation in the reg to output paths. When i tried to debug these paths, i found that clock network delay for the capture clcok is zero.
So, i think that i have a problem with the clock latency, and i am confused about how can i specify the proper clock latency, and is this in the synthesis stage or post-cts?
Can anyone help me ?

Thanks
 

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