[#define F_CPU 11059200UL
#include<avr/io.h>
#include<util/delay.h>
#define BAUD_RATE 71
//DEFINING THE SPI PORT OF MICROCONTROLLER
#define DDR_SPI DDRB
#define SCK 7 //PORTB.7
#define MISO 6 //PORTB.6
#define MOSI 5 //PORTB.5
#define cbi(port,bit) (port)&=~(1<<(bit))
#define sbi(port,bit) (port)|=(1<<(bit))
void INIT_SPI(void);//initializing the spi of the uP
void ADNS_WRITE(unsigned char,unsigned char);//writing to adns (data,address)
unsigned char ADNS_READ(unsigned char);//reading from adns inputting the address of register and getting data
void SPI_INIT(void) //INTIALIZATION OF SPI
{
SPCR=(1<<SPE)|(1<<MSTR); //ENABLE SPI AND MAKE IT MASTER
SPCR|=(1<<CPOL); //it 0 CLOCK TRALLING EDGE IS 1, LEADING EDGE IS 0
SPCR|=(1<<SPR0); // SELECTING MODE 2 FOR SCLK (Fosc/16)
SPCR&=~(1<<DORD); //MSB FIRST DORD=0,LSB=1
SPCR&=~(1<<CPHA); //SETING BIT ON FALLING EDGE OF SCLK CPHA=0
DDR_SPI&= ~(1<<MOSI) & ~(1<<MISO);//MAKING MISO AND MOSI INPUT FOR TRISTAING IT
PORTB|=(1<<MISO)|(1<<MOSI);//TRISTATING BOTH MISO AND MOSI
DDRB|=(1<<SCK);//MAKING SCK OUTPUT AFTER MOSI AND MISO IS TRISTATING TO OVERCOME SYNC PROB
}
// MINIMUM DIFF B/W TWO WRITE SHOULD BE 100usec
void ADNS_WRITE(unsigned char addr,unsigned char data)
{
SPCR&=~(1<<CPHA); //SET BIT ON FALLING EDGE
addr|=(1<<7);//MSB OF ADDRESS SHOULD BE 1 IN WRITE OP
SPDR=addr;
DDR_SPI|=(1<<MOSI);//OPENING MOSI
while(!(SPSR & (1<<SPIF)))
{}
SPDR=data;
while(!(SPSR & (1<<SPIF)))
{}
DDR_SPI&=~(1<<MOSI);//MAKING MOSI INPUT FOR TRISTAING IT
PORTB|=(1<<MISO)|(1<<MOSI);//TRISTATING THE MISO AND MOSI PIN BY WRITING PORT=1
}
// THE MINIMUM DIFFERENCE BETWEEN TWO READ OR WRITE SHOULD BE 250ns
unsigned char ADNS_READ(unsigned char adr)
{
SPCR&=~(1 << CPHA); //SETTING DATA ON LEADING EDGE OF CLOCK
adr &=~(1<<7); //MSB OF ADDRESS SHOULD BE 0 IN READ OP
DDR_SPI|=(1<<SCK);
DDR_SPI|=(1<<MOSI);
SPDR=adr;
while(!(SPSR & (1<<SPIF)))
{}
//HOLD LAST BIT OF ADDRESS FOR MORE THAN 250ns
DDR_SPI&= ~(1<<MOSI);
PORTB|=(1<<MOSI);//MAKING MISO HI-Z
SPCR&= ~(1<<CPHA);
_delay_ms(1);//DELAY SO THAT ADNS-2610 CAN PREPARE DATA
SPCR|=(1<<CPHA);//Up will read on rising pulse of sck
PORTB&= ~(1<<MISO);//CHANGI MISO FROM TRISATE TO INPUT PIN
DDR_SPI|= (1<<SCK);
while(!(SPSR & (1<<SPIF)))
{}
DDR_SPI&= ~(1<<MISO);
PORTB&= ~(1<<MISO);
return SPDR;
}
color=blue][/color]