always @(posedge clk or posedge reset or posedge enable)
begin
if (reset)
out <= 1'b0;
else if (enable)
out <= 1'b1;
else
out <=a & b;
end
always @(posedge clk or posedge reset or posedge enable)
begin
if (enable)
out <= 1'b0;
else if (reset)
out <= 1'b1;
else
out <=a & b;
end
I am a VHDL person, but this looks like bad code that can cause a mismatch between simulation and synthesized hardware.
If you activate both reset and enable, and then release one of them, the simulator will not do anything at the release.
The hardware for the first design (if accepted by the synthesis tool) will change the output from '0' to '1' if both reset and enable are '1', and reset then changes to '0'.
I agree with std_match, there's a potential simulation mismatch with this code, as discussed in previous Edaboard threads, e.g. https://www.edaboard.com/showthread.php?321110-Sensitivity-lists-syntax-in-VHDL-and-Verilog
Hardware synthesis can be expected to follow the known register template and creates asynchronous set and reset function with priority. Deasserting the reset will allow the lower priority set input to take effect if it's already asserted. However in simulation, there's no event created when the reset input is deasserted, due to the fact that the register template doesn't literally correspond to the intended function. (Correct functional simulation would require level sensitive events, but they are accepted by synthesis tools…)
I assume so far that your ASIC synthesis tool can implement the priority of asynchronous inputs correctly. Newer FPGA hardware is often lacking an asynchronous set input and needs to emulate the described logic with latches.
assign enable_int = ~reset & enable;
always @(posedge clk or posedge reset or posedge [B]enable_int[/B])
begin
if (reset)
out <= 1'b0;
else if (enable)
out <= 1'b1;
else
out <=a & b;
end
I guess there's a typo in post #7. This construct complies with the register template and should work in functional simulation as well:I have tried similar code in system verilog (always_ff) with synopsys DC (we have only active low S, R) and the result is S-R FF with correct priority.
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 assign enable_int = ~reset & enable; always @(posedge clk or posedge reset or posedge enable_int) begin if (reset) out <= 1'b0; else if (enable_int) out <= 1'b1; else out <=a & b; end
cannot match operand(s) in the condition to the corresponding edges in the enclosing event control of the always construct
No, it is not the typo. I really used it as I wrote in #7.
Originally I wrote it as model and wanted to replace it with cell from the library during the synthesis. But after the synthesis I saw, that DC recognized it properly (no warnings, internal signal removed and enable connected to the set).
I am not sure wether enable_int will be removed during optimization or not when it is used in the condition itself.
I know that it is not in line with the register template, but Verilog/System Verliog don't have an alternative to clock event as VHDL and so I use this as workaround. I also don't know if it will work properly with other tools. It needs to be tested.
As I mentioned, another way might be:
- You can use `ifdef for sensitivity list to distinguish between synthesis and simulation.
- Write it into a separate module and replace it with library cell during the synthesis.
else if (enable)
else if (enable_int)
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