primetime report, help?

[quan228228]

The following are primetime report:

Startpoint: cheetah_top/u_mcu/i_core/i_cpu/i_biu/ale_neg_reg
(rising edge-triggered flip-flop clocked by clk30')
Endpoint: ALE (output port clocked by clk30)
Path Group: outputs
Path Type: max

Point Incr Path
------------------------------------------------------------------------------
clock clk30' (rise edge) 16.00 16.00
clock network delay (propagated) 5.61 * 21.61
cheetah_top/u_mcu/i_core/i_cpu/i_biu/ale_neg_reg/CK (FFSDRHD4X)
0.00 21.61 r
cheetah_top/u_mcu/i_core/i_cpu/i_biu/ale_neg_reg/QN (FFSDRHD4X)
0.36 * 21.97 f
cheetah_top/u_mcu/i_core/i_cpu/i_biu/U120/Z (NAND2HD4X)
0.12 * 22.09 r
cheetah_top/u_mcu/i_core/i_cpu/i_biu/mem_ale (VEO_DW8051_biu_rom_addr_size13_1)
0.00 * 22.09 r
cheetah_top/u_mcu/i_core/i_cpu/mem_ale (VEO_DW8051_cpu_ram_2561_rom_addr_size13_extd_intr1_1)
0.00 * 22.09 r
cheetah_top/u_mcu/i_core/mem_ale (VEO_DW8051_core) 0.00 * 22.09 r
cheetah_top/u_mcu/ale (veo_8051) 0.00 * 22.09 r
cheetah_top/U843/Z (AND3HD4X) 0.29 * 22.38 r
cheetah_top/ale_out (cheetah_top) 0.00 * 22.38 r
PAD_ALE/I (PB4W_13) 0.00 * 22.38 r
PAD_ALE/U1/Z (BUFHD20X) 0.19 * 22.57 r
PAD_ALE/PLBI4N_ins/P (PLBI4N) 1.66 * 24.23 r
PAD_ALE/PAD (PB4W_13) 0.00 * 24.23 r
ALE (inout) 0.00 * 24.23 r
data arrival time 24.23

clock clk30 (rise edge) 32.00 32.00
clock network delay (propagated) 0.00 32.00
clock uncertainty -0.15 31.85
output external delay -10.00 21.85
data required time 21.85
------------------------------------------------------------------------------
data required time 21.85
data arrival time -24.23
------------------------------------------------------------------------------
slack (VIOLATED) -2.38


/////////////////////////////////////////////////////////////////////////////////
The register (start point) is trigged by rising edge of clock "clk30". The output "ALE" is also clocked by clock "clk30".
Why the timing calculation starts from 16 (the negedge of clk30)?

Thanks!
David

 

[spauls]

This is a half cycle path and also your constraints are high.

 

[Thinkie]

You can notice a small tick on the starting clk30'

This means that your (FFSDRHD4X) is clocked using the negative edge of the clock. therefore at 32/2=16 assuming you didn't specify a waveform mark to space ration

 

[yln2k2]

Hi ,

As mentioned in the pervious reply at Start point clk has "clk30' " which means start point is clock inverted and it is half cycle path .

please check the report with clk as full expansion .


Thanks & Regards
yln

 

[quan228228]

Thanks for your help.

I dump the waveform and find the clock "clk30" is inverted from source clock. So this is a half cycle path.


Thanks again.

David.

 

[rameshsuthapalli]

this is the half cycle path and it is C2O path dont worry the chip will work but take care about the external delay.

regards,
rameshs