[SOLVED] PrimeTime Power-Driven Timing Analysis

[gepinita]

I am setting the voltage of each cell in the design by using the following command :

set_voltage 0.9884 -cell instancename -pg_pin_name VDD

I am performing timing analysis but i get the same results with the nominal voltage timing analysis.
I want to perform a power driven timing analysis based on the new values that i have set and not on the nominal voltage of the design library i use.
Does anyone know how can i do this?

Thank you in advance.

 

[oratie]

Usually, you should use several libraries, to perform STA with IR-drop data. One library is characterized for nominal voltage, the others (other) for non-nominal voltage.

set power_enable_analysis true
read_verilog
define_scaling_lib_group {lib1 lib2}
set_rail_voltage ...
report_timing -voltage ...

 

[gepinita]

Thanks oratie for your prompt response... I will check this and I will inform you...

 

[gepinita]

I am setting the rail voltage in each cell and I am using Nangate Typical, Slow and Fast libraries for interpolation. But the result i get has larger timing delay than the one characterized with the slow library...
That isn't logical... What's going on?

Thank you in advance.

 

[oratie]

You can not use Typ, Slow and Worst libraries together to perform STA with IR-drop info. Because, the difference between these libs are in different transistor model, different temperature and different voltage.

You should have additional libs, that have difference only in voltage.
For example: define_scaling_lib_group { tcbn65lphvt_wc.db tcbn65lphvt_wc07.db }
Where both these libraries used SS model of transistors, 125C as a temp, and the first one was characterized at 0.9V and the second at 0.7V.

 

[gepinita]

Oratie you have been very helpful... Thank you very much...