Hello,
i have done the synthesis of a design and after that i want to measure its power consumption with PrimeTime.
The only warnings i get are : Warning: There are 567 out_of_range ramps.
Warning: There are 106 out_of_range loads.
can i ignore them?i have tested the design in modelsim and it seems to operate fine.
Thank you in advance.
NO you can't.
Your std cell library has requirements for max transition times at input pins and max load at output pins. you have to tell synthesis about those, so a DRV-free design can be generated.
you have to fix those or the power value calculated is somewhat meaningless.
So what may generate these warnings?Do you have any advices on what i can do to eliminate them?I searched but i found nothing helpful so far...
The only warnings i found in modelsim were some vital glitches and they did not occur on the input-output ports of my design so i ignored them.
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"there's also a chance that you set no output load for IOs and/or ideal inputs. those would cause out_of_range warnings too."
in order to set output load i use this command "set_load $normal_load [all_outputs]" ?
about the loads: if these are primary outputs of the circuit, they will be connect to pads. you can use the capacitance of the pad as the output load.
How can i do this?i am using library 90nm UMC.How can i know the capacitance of the pad??
Could you explain me a bit more also your point "- you must set the transition time of the primary inputs of your circuit so they don't look ideal. usually what we do is we tell the synthesis tool what a fictitious driver would look like. ie, tell the tool that the primary input of your circuit behaves as the output of an inverter X1." . I understood the rest.
Thank you
point #1: do you have a pad library? It is a secondary library, it doesn't come with your standard cells. If you have, the cap values are inside the .lib file of the pad library. you use that value with the set_load command
about point #1:Here is my library file but i cannot understand what the load i should set to my design..Could you please tell me how can i find this?I do not see anything like "pad capacitance = ".
I'm afraid you didn't understand my initial point. I asked if you have a pad library. The file you just posted is a standard cell library.
No,this is my only library..Should i have one?
About point#2: Thanks,now i understood why i must do this.Also by setting the inputs to drive 0.2 pF ,then my out_of_range ramps are reduced to 350.
If my design is using 3 components,should i do this for every of these components , or only to the primary inputs of my design?
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Ramp time is the time a signal need to change its inputs??so if the warn says ramp 0.00 at pin 'C1' of cell 'slavefabric/aw_1/u37' is out of ramp range (0.01, 0.78) of lib_cell 'AOI222X1' it means that the ramp time is zero,and this cannot happen?if so,how can i raise my ramp time?
Please if someone knows..i struggle with this for days..
If you don't have pads then you can't really build a chip. It is fine for some early circuit analysis and rough evaluation of power and timing.
about ramp times: when your standard cells were characterised, the vendor had to do so for a range of input slopes (ie ramps that are as fast as 0.01 or as slow as 0.78). 0.0 is not in that range, because it is artificial. to raise your ramp time, you have to model the signal slope.
Right. That command should be enough.
For the warnings that you are still seeing it would be necessary to trace back the logic. Maybe there is some other issue somewhere else. Do you have memories in your design?
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