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Practical Timing simulation...

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Member level 3
Nov 5, 2007
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While designing circuits, We cannot synthesise timing delays. Model sim is used to have timing simulation( ie ideal response). I think so. But how to have a timing simulation in practical cases, ie, including timing constraints defined for the device. is there any other simulation software to do this.
pls help me regarding this..

Thanx in advance

Normally you apply timing constraints that specify your required clock frequency, setup times, maximum skew, etc. The synthesis and place-n-route tools will try to achieve those constraints. If the tools were successful (no unhappy timing messages), and if your constraints were thorough, then your design should work reliably.

You could also run a post-route simulation to see the design run with all the estimated propagation delays, but that's not necessary in many projects.

Hi angu.

In my opnion, u need to understand the ASIC design flow first.
Then, u'll know where and how to do it.

Basically, u have ur RTL code.
Next, perform RTL simulation (called Functional Simulation or pre-synthesis simulation)
Once you get the code and functionality is correct. U need to synthesize the RTL code. Whether it is using ASIC library or FPGA library upto the Designer.

After tht u'll get gate-netlist circuit or synthesized circuit.
Next, u take this gate-netlist circuit and perform another simulation called Timing Simulation (Post-synthesis simulation).

Now, u'll have a gate delay. Not so accurate. But good enough to check ur circuit performance. To get more accurate timing information, u need to do layout design and do parasitic extraction.

I hope u get what I'm trying to say here.

The best is u need to have an ASIC flow chart. U can get this from any ASIC books or just google it.

Hope it helps.

There are three widely used simulators.

Modelsim, Cadence NCVerilog and Synopsys VSS.

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