Power stage small sighnal transfer function for current mode CCM synchronous Buck?

[treez]

Hello,
We are calculating the feedback loop (gain & phase margins) for a Current Mode, Synchronous Buck Converter which is in CCM at full load.
When on no load, the Sync Buck still has “continuous” inductor current, ..so, for evaluating the Power Stage transfer function when on no_load, do we use the equation for a “discontinuous” current mode buck, or the equation for a “continuous” mode current mode buck?

 

[Easy peasy]

At no load the current is not continuous (in a sense) in the inductor in the output direction (it is AC, with zero crossings, OK it might be considered continuous, but AC), thus there are subtle differences if you use the SS TF for the continuous case.

The TF now has a heavy dependence on the ON time of the lower FET, which may not appear at all in your TF.

Increasing the ON time ever so slightly of the lower fet (at no load) will cause net reverse power flow and a lowering of Vout, it would be easy for a system to be some what oscillatory here... as there is no load and very little damping on the o/p...
There would be appreciable AC current in the o/p caps also - not so desire-able...

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Ideally at no load, both devices should be running a duty cycle of zero, with a little bit of pulse skipping (burst mode) every 0.5 sec to keep the output up, top device only, 0.5% on time, burst length designed to get o/p to Vout + 5%, then off...until Vout falls to Vout x 0.95...

This action is taken from a slow error amp...

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or simply disable switching the lower fet for currents less than 5% of Imax, (app dependent)

 

[FvM]

In a first order estimation, the modulator and power stage transfer function of a synchronous buck or boost converter is current independent. Use CCM equations.

 

[treez]

In a first order estimation, the modulator and power stage transfer function of a synchronous buck or boost converter is current independent. Use CCM equations.

thanks, even for the case of no_load?

 

[mtwieg]

Yes, it's the same, both for CMC and VMC loops. The AC transfer functions are independent of the DC operating points.

 

[treez]

thanks, yes I appreciate they are the same for VMC and CMC, but is a synch buck (with AC current in its inductor) , which is synchronous in no_load, having the same small signal transfer function as a non synchronous Buck converter in no_load?

 

[mtwieg]

No, non-synchronous case will have a nonlinear transfer function when operating in DCM. For the synchronous case with forced CCM operation, there is no such nonlinearity (for a buck converter anyways).

 

[treez]

thanks, so you really are saying that a current mode , synchronous Buck converter in no_load (with AC current in its inductor), has to be dealt with by the same equation that gets used for a non-synchronous, CCM , current mode buck converter?

 

[treez]

The strange thing is that the attached LTspice simulation of a current mode synchronous Buck converter is perfectly stable at full load, but goes unstable at no load (you can see this by running it with and without a load).
This finding (instability in no_load), supports what Easy Peasy (in post #2) has said about the problem of gaining stability with a synchronous Buck converter in no_load......

Increasing the ON time ever so slightly of the lower fet (at no load) will cause net reverse power flow and a lowering of Vout, it would be easy for a system to be some what oscillatory here... as there is no load and very little damping on the o/p...

......try whatever feedback compensation components that you like, you will not be able to make this (attached) current mode synchronous buck simulation stable in no_load...any explanation for that?

 

[FvM]

Problem is LT1243 not being designed for sync buck converters, allowing uncontrolled blanking of the output pulses for an extended time.

Apparently the circuit is instable with resistive load, too.

 

[mtwieg]

A quick glance makes it obvious that it's not a small-signal oscillation, and is therefore due to nonideal behaviour of the controller. It occurs because the controller can't control the peak current when the peak current is negative (and therefore can't control the average current when the average drops below -ΔI/2). Increasing ΔI by decreasing the inductor to 50uH causes it to avoid this in your simulation.

 

[treez]

thanks, indeed you are right FvM and Mtwieg, the controller does not ensure that the sync fet always stays on for less than one switching period. And as Mtwieg says indeed the error amp control voltage is not able to go low enough to control it in light load with such a high inductor value.

Apparently the circuit is instable with resistive load, too.

thanks, but the simulation is stable in full load, as in the following
https://www.edaboard.com/threads/349575/