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Power sequence question on this IC

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The datasheet - KSZ8463 for this says that a power-on sequence where the higher voltage rails come up before (or with) the low voltage ones is "recommended".

Could you tell me the reason for the recommendation? Would it cause a reliability problem if this is not followed, or would it be something more minor (ie, increased power consumption, or the device will need to be reset after power-on)?

The specific condition I'm considering is where all rails except VDD_A33 ramp up together, but VDD_A33 ramps up a few ms later.

My thoughts:

In section 3.9.1, page 49, 50, it says, that the VDDIO and the VDD_D3.3 only powers the internal low core voltages. So, if we power the low core voltages first, externally, and then the VDDIO/VDD3.3A, then wouln't there be a leakage back from the low voltage path to the 3.3/2.5/1.8V VDDIO/VDD_3.3 path?
 

The answer to this has to come from designers/tech support at Microchip.

Looking at the comments and footnotes on the power sequence its pretty clear
they want customer to follow those recommendations. Unfortunately not adding
reasons why. But I would be inclined to follow the datasheet, there clearly is concern
about chip operation expressed in the constraints shown.

While you are waiting you could always do some bench testing to see if part latches
up, a common issue in sequencing, which generally raises power consumption dramatically.
If high enough could blow open internally supply bond wires and current draw falls to 0
hence catastrophic failure.

Power sequencing could also be hiding a chip design flaw that was not taken care of,
so they went to market early.....would not be the first time this was done in industry.

If you need sequencing there are a number of possibilities, this being one of them (single
chip. this is just a tiny fraction of whats on this SOC)

1670590954800.png



Regards, Dana.
 
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