power measurement in different process technology

[william_luo]

Hi,

I have a question about power measurement by cadence virtuoso.
I measured static power and total power for a circuit (like ripple carry adder in 15nm and 45nm process technology, and both used Nangate Open Cell Library and ASU PTM model card). We know that the static power should account for a significant portion of the total power when a small size process is used, say 15nm. But I did not see this in my simulation. I found that the proportion of static power in total power (15nm) is even similar with that under 45nm process. In addition, the total power obtained in 15nm is even bigger than in 45nm process. The good side is that the timing delay in 15nm is much smaller than in 45nm process. Can someone help me explain the power part? Is it all because of the model cards I used in my simulation? Thanks!

Regards,
Wayne

 

[erikl]

... We know that the static power should account for a significant portion of the total power when a small size process is used, say 15nm. But I did not see this in my simulation. I found that the proportion of static power in total power (15nm) is even similar with that under 45nm process.

I don't know if your analysis considers the layout area, but if it does so, this could explain the result: leakage current per area may be larger at 15nm, but the area size is smaller.

In addition, the total power obtained in 15nm is even bigger than in 45nm process. The good side is that the timing delay in 15nm is much smaller than in 45nm process. Can someone help me explain the power part? Is it all because of the model cards I used in my simulation?

Just a guess: In an (essential) digital circuit, faster edges generate more harmonics, so consume more power (which mainly is radiated).

Of course the model cards are responsible for these results. That's what is expected from them: analysis results as close to reality as possible, isn't it? ;-)

 

[william_luo]

Thanks for your quick rely, erikl.
Actually, I did not consider the layout part. All of my designs are just based on schematic. I found model cards with two modes (high performance(hp) and low stand-by power (lstp) mode) on the webpage of ptm.asu.edu. If I do the simulation in the hp mode, I will get a much higher power consumption than the lstp mode I used before.

Thanks!
Wayne