power estimation using cadence rc

Hi all,

I got a question about power estimation using cadence rc.

I have two designs in HDL. Both of then have a 1-bit full adder. After synthsis, and post-simulation the netlist with the same test data, I found the output toggle rate of these two 1-bit full adder are different, even though they have exactly the same input toggle rate. What could be the reason that the output toggle rate are different? Thanks~


============================
1-bit full adder in Design 1 (tcf file):
============================
instance("FA0_15") {
pin() {
"A" : "0.747505 390";
"B" : "0.240519 372";
"C" : "0.256487 384";
"Cout" : "0.342315 454";
"SUM" : "0.559880 478";
}
instance("g58") {
pin() {
"A" : "0.240519 372";
"B" : "0.747505 390";
"CI" : "0.256487 384";
"S" : "0.559880 478";
"CO" : "0.342315 454";
"n2" : "0.183633 320";
"n3" : "0.050898 98";
"n4" : "0.185629 312";
}
}
}

============================
1-bit full adder in Design 2 (tcf file):
============================
instance("FA0_15") {
pin() {
"A" : "0.747505 390";
"B" : "0.240519 372";
"C" : "0.256487 384";
"Cout" : "0.342315 538";
"SUM" : "0.559880 838";
}
instance("g62") {
pin() {
"A" : "0.240519 372";
"B" : "0.747505 390";
"CI" : "0.256487 384";
"S" : "0.559880 838";
"CO" : "0.342315 538";
"n2" : "0.183633 382";
"n3" : "0.050898 98";
"n4" : "0.185629 390";
}
}

======================================
both g58 and g62 are the instance of "FA1D0":

FA1D0 g58(.A (B), .B (A), .CI (C), .CO (Cout), .S (SUM));
FA1D0 g62(.A (B), .B (A), .CI (C), .CO (Cout), .S (SUM));