Is it possible to estimate the power of our vhdl implimented design. apart from system parameters it depends on technology. Is there any tool which can estimate for power on a required clock and technology for ASIC for ceratin no. of operations?
You'd better estimate the power at gate level. And you should alos privide a SAIF(from simulation toll based on your pattern) like file to let the tool know the toggle possibility of the netlist.