Power Circuit Analysis using HSPICE Verilog-A Models

[alexdeus]

Hello to all, i dont know if this is exactly the section in which i can put my req topic.
I have a problem in digital circuit analysis.
I have Verilog-A models of cnfet transistor, and i wish analyze elementary logic cells with HSPICE.
The problem is that with Verilog A models, i cannot use the .meas POWER() statement for determining power consuption of the cell.
Does anyone know how can i do this in the hspice netlist of my circuit?
HSPICE manual is not helpful.
Thank you very much for answering!

Alessandro

 

[erikl]

If the .va model includes the modeling of the drain current (which it really should!), you could probe the Id current flowing into the FET, as well as the drain-source voltage Vds.

 

[dick_freebird]

You can put trivial resistors at the power ports to read
the current. Trick is in determining the load and through-
current, if that matters, but for logic you can call it all
a loss. You could do something like a ring oscillator, let
it run and pull the main supply current and divide by N.

 

[alexdeus]

Thank you very much to all for your replies.
I just thought to probe the supply avg or rms current, then i multiply this value of current per supply voltage, i think that in this way i can obtain the total avg or rms power of the cell.
I mean:

.MEAS TRAN IDDAVG AVG I(VDD)
.MEAS TRAN IDDRMS RMS I(VDD)
.MEAS POWERTOTRMS PARAM='IDDRMS*V(VDD)' *total RMS power of the cell
.MEAS POWERTOTAVG PARAM='IDDAVG*V(VDD)' *total AVG power of the cell

instead of:

.MEAS TRAN POWERTOTAVG AVG POWER *total AVG power of the cell
.MEAS TRAN POWERTOTRMS RMS POWER *total RMS power of the cell

What do you think about this? Do you think it can be a correct value?
Thank you very much,

Alessandro