Power Aware Signal Integrity Analysis of SerDes and DDR4 Interfaces.

[anilkrpandey]

Do we need Power-Aware Signal Integrity Analysis in SerDes ?

I know in parallel high-speed digital interfaces like DDR4 we do power-aware SI analysis but do we need Power-Aware Signal Integrity Analysis in SerDes interfaces also like in PCIe.

Power-Aware signal integrity analysis of DDR4 data bus is necessary for the channel reliability and robustness. In high- speed digital (HSD) boards due to simulation tools limitation, power integrity, and signal integrity analysis are performed separately. The complete data channel performance is the cumulative effect of whole interconnect environment that consists of transceiver ICs, power planes, bond wires, board substrate, data lines and board interconnects that’s why it’s necessary to consider power plane generated noise effect in data channel signal integrity analysis.

But Is same true for SerDes ( USB, SATA, PCIe....) Interfaces also?

 

[Airbag79]

SERDES is not as sensitive to Common-Mode Noise due to differential topology. It's more critical in DDRx application because data is single-ended and there is a a lot of SSN. Albeit, it's never a bad thing to incorporate non-ideal Power and GND in your simulations, as it will be more accurate.