I have no idea what do you want to achieve (what is expected functionality of this circuit), however:
1. current flowing through Q2 is set to (VCC-VBE)/1MΩ what gives you values between ≈0 and 4µA for VCC in range 0.5 - 5V
2. Q1/Q2 ratio is ca 8, so VBE1≈VBE2-60mV. It means, that you would like to force Q1 emitter current to ca 60nA. However, at some point (quite early) your Q1 has no space for VCE and is going to saturation. It means, that your nodeB is following the voltage divider with division ≈0.5. The impedance at nodeB is 500kΩ, what with gate cap of MN1 (suppose ca 5fF) gives you negligible for your slope time constant of ca 2.5ns.
3. NodeB is quickly forcing MN1 to pull-down nodeC to ground, making vout equal to VCC.