POW circuit design

[Myself1247]

need to design a POR circuit with Vdd= 1V-5.5V, supply current= 1-1.5 micro A, trigger voltage= 0.6-0.9V without BGR and 2 input supply ramp, there should be output only when both the inputs cross the trigger point.

 

[barry]

Are you telling us that because you thought we'd be interested to know what you're doing, or are you just asking somebody else to do your job/homework for you without showing a single bit of effort on your part?

 

[Myself1247]

Are you telling us that because you thought we'd be interested to know what you're doing, or are you just asking somebody else to do your job/homework for you without showing a single bit of effort on your part?

I have already designed a transistor level design for the same but my supply current ranges from micro to milliamps. So i was basically asking for help. And to answer your part I have done my homework brother and no i have spent 20 days thinking and designing the circuit. So if you cannot help please don't discourage people from helping one another.
Peace

 

[KlausST]

Hi,

Barry just asked questions ... where your information was not clear.
Still you don´t show what you have done so far.
Barry does not discourage other people from helping you.

You write
* "need to design" ... the first I thought: Who? We or you?
* "I have already designed" .. but we don´t see it
* "I was asking for help". Please clarify: In which regard do you need help?

Klaus

 

[barry]

Hi,

Barry just asked questions ... where your information was not clear.
Still you don´t show what you have done so far.
Barry does not discourage other people from helping you.

You write
* "need to design" ... the first I thought: Who? We or you?
* "I have already designed" .. but we don´t see it
* "I was asking for help". Please clarify: In which regard do you need help?

Klaus

To elaborate, I don't discourage people from helping others, despite the fact that they've shown no effort by, at the very least, posting an intelligent, well thought out question. But I, for one, am not inclined to help them.

I don't care if you've spent 20 years "thinking and designing" your circuit. You've shown us nothing. You are asking for help without stating what you need help with. Your post reads like "I need a circuit to do this function. Design it for me."

People on this forum are EXTREMELY helpful. There is a wide range of knowledge here. But we resent when people come prancing in here expecting us to solve their problems without showing any effort of their own.

 

[Myself1247]

I am sorry for my actions. I have designed the circuit for a trigger voltage of 0.7-0.9V and also the supply current should be in the range of 1-2uA, but i have some encountered some doubts.

1.the trigger voltages changes for different input ramp rate. I first applied a rise time for 10usec the trigger voltage came around 0.9V . Now when i decreased the ramp time to 5usec the trigger voltage moved to 1.6V.
could you help me understand how the input ramp rates affect the trigger voltage(in this circuit)?

2.The node B voltage behaves as a delayed ramp input to a RC circuit. How is this circuit actually behaving in such manner?

3. How can i use hysteresis to providing noise immunity to sudden fluctuations of supply voltage?
Could you provide any suggestions for improving the circuit.

 

[Dominik Przyborowski]

I have no idea what do you want to achieve (what is expected functionality of this circuit), however:
1. current flowing through Q2 is set to (VCC-VBE)/1MΩ what gives you values between ≈0 and 4µA for VCC in range 0.5 - 5V
2. Q1/Q2 ratio is ca 8, so VBE1≈VBE2-60mV. It means, that you would like to force Q1 emitter current to ca 60nA. However, at some point (quite early) your Q1 has no space for VCE and is going to saturation. It means, that your nodeB is following the voltage divider with division ≈0.5. The impedance at nodeB is 500kΩ, what with gate cap of MN1 (suppose ca 5fF) gives you negligible for your slope time constant of ca 2.5ns.
3. NodeB is quickly forcing MN1 to pull-down nodeC to ground, making vout equal to VCC.

 

[Myself1247]

I have no idea what do you want to achieve (what is expected functionality of this circuit), however:
1. current flowing through Q2 is set to (VCC-VBE)/1MΩ what gives you values between ≈0 and 4µA for VCC in range 0.5 - 5V
2. Q1/Q2 ratio is ca 8, so VBE1≈VBE2-60mV. It means, that you would like to force Q1 emitter current to ca 60nA. However, at some point (quite early) your Q1 has no space for VCE and is going to saturation. It means, that your nodeB is following the voltage divider with division ≈0.5. The impedance at nodeB is 500kΩ, what with gate cap of MN1 (suppose ca 5fF) gives you negligible for your slope time constant of ca 2.5ns.
3. NodeB is quickly forcing MN1 to pull-down nodeC to ground, making vout equal to VCC.

I have basically designed a POR circuit with trigger voltage of 0.9V. the values of R0, R1, R2 are taken to set the trigger voltage to a particular voltage and also my supply current requirement is 1-2uA so i have used MOhms of resistors. Could you please elaborate how there is no space for Vce. Also if the time constant of the RC is much smaller than my input ramp rate(5us) then the node B voltage should follow the input supply but why there is a huge gap between them?

 

[Dominik Przyborowski]

Could you please elaborate how there is no space for Vce.

Simply check net2 voltage.
What can be responsible for dynamic of the circuit is the tempo of biasing the bipolar. It is clearly seen on nodeA voltage.

//edit
One of the workaround might be adding 100fF cap in parallel to R0, it should inject ca 1uA Current i to Q2 during VCC ramping and boost the speed.

 

[D.A.(Tony)Stewart]

Your schematic will never show the Gate input capacitance and rise time delays. I won't try to correct the discrete configuration and instead suggest you consider POR CMOS solutions in IC's or properly define your objective design specs and use low current high speed comparators.

--- Updated Sunday at 1:12 AM ---

This is a far simpler design that does not have the large Ciss delays of FETS with large gate R's

Threshold 0.8V +/-10% (792 mV @ 25'C)

https://tinyurl.com/2o4xxuuq

Beware of pF loading effects on risetime.

 

[Myself1247]

I am ramping the supply at 10usec/V for two inputs 1.08V and 3.6V and the trigger point only occurs when both the inputs cross the threshold. i have done the simulation but the output goes to negative voltage of some mV. why is it happening?