I'm exploring potting high voltage, low power PCBs (~5kV) and the possible reduction in distance between components.
After potting a PCB with a good CTI in a low pollution environment, do you have to consider the effects of tracking between components along the boundary between the potting compound and the surface of the PCB, or can it be completely ignored?
It sounds too good to be true - once there is no longer any pollution, the limiting factor is the breakdown of your materials, which can be in the order of kV's/mm making the layout tiny!
I'm guessing there is more to it, it would be great to know what your thoughts are!
i suggest you do consider the possibility of arcs between the PWB and the potting compound
i have seen a high voltage unit fail when it arced right along the boundary
between the transformer oil insulator and the fiberglass PWB
we ended up cutting a slot in the PWB, thereby lengthening the path, or forcing the arc to go through the oil
problem solved
IEC 1010 is requiring 1.5 mm distance at 5 kV working voltage between conductors on the same layer for moulded and potted parts, the same as for inner PCB layers. Obviously, a homogenous interface between PCB and potting material is presumed.
It should be noted that IPC 2221 6.3 is suggesting a clearance as high as 11.5 mm at 5 kV for internal conductors. The numbers aren't substantiated in the standard. We can guess that they consider failure mechanisms like CAF (conductive anodic filament growth). In other words, you should worry more about internal voltage strength of the PCB than of the molding, at least with standard FR4 PCB.
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Internal horizontal PCB clearance requirements, IEC1010 versus IPC
i suggest you do consider the possibility of arcs between the PWB and the potting compound
i have seen a high voltage unit fail when it arced right along the boundary
between the transformer oil insulator and the fiberglass PWB
we ended up cutting a slot in the PWB, thereby lengthening the path, or forcing the arc to go through the oil
problem solved
Thanks! It does look like with these kind of potting and encapsulation techniques, you either do have very good insultation or it's failed and it's all gone - there's no in-between. I'll see if I can design in some slots so the epoxy is more like a barrier.
IEC 1010 is requiring 1.5 mm distance at 5 kV working voltage between conductors on the same layer for moulded and potted parts, the same as for inner PCB layers. Obviously, a homogenous interface between PCB and potting material is presumed.
It should be noted that IPC 2221 6.3 is suggesting a clearance as high as 11.5 mm at 5 kV for internal conductors. The numbers aren't substantiated in the standard. We can guess that they consider failure mechanisms like CAF (conductive anodic filament growth). In other words, you should worry more about internal voltage strength of the PCB than of the molding, at least with standard FR4 PCB.
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Internal horizontal PCB clearance requirements, IEC1010 versus IPC
That is an incredible difference between the two standards, this is for a measurement system so it looks like we could push it into a very small package.
It's looking like creepage is no longer the problem and, as you say, I should be looking more into other failure modes such as breakdown/CAF.
the biggest issue is voids, all the E field concentrates over a void - if the material breaks down to SiO2, i.e glass, then the voltage withstand will be OK, if it breaks down to a carbon compound - then things tend to get worse ....