Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Potting High Voltage PCBs

cdpstu

Newbie
Joined
Jul 2, 2021
Messages
2
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
21
Nice to meet you all,

I'm exploring potting high voltage, low power PCBs (~5kV) and the possible reduction in distance between components.

After potting a PCB with a good CTI in a low pollution environment, do you have to consider the effects of tracking between components along the boundary between the potting compound and the surface of the PCB, or can it be completely ignored?

It sounds too good to be true - once there is no longer any pollution, the limiting factor is the breakdown of your materials, which can be in the order of kV's/mm making the layout tiny!

I'm guessing there is more to it, it would be great to know what your thoughts are!
 

wwfeldman

Advanced Member level 3
Joined
Jan 25, 2019
Messages
856
Helped
201
Reputation
401
Reaction score
220
Trophy points
43
Activity points
6,319
i suggest you do consider the possibility of arcs between the PWB and the potting compound
i have seen a high voltage unit fail when it arced right along the boundary
between the transformer oil insulator and the fiberglass PWB

we ended up cutting a slot in the PWB, thereby lengthening the path, or forcing the arc to go through the oil
problem solved
 

FvM

Super Moderator
Staff member
Joined
Jan 22, 2008
Messages
48,519
Helped
14,272
Reputation
28,807
Reaction score
12,976
Trophy points
1,393
Location
Bochum, Germany
Activity points
280,609
IEC 1010 is requiring 1.5 mm distance at 5 kV working voltage between conductors on the same layer for moulded and potted parts, the same as for inner PCB layers. Obviously, a homogenous interface between PCB and potting material is presumed.

It should be noted that IPC 2221 6.3 is suggesting a clearance as high as 11.5 mm at 5 kV for internal conductors. The numbers aren't substantiated in the standard. We can guess that they consider failure mechanisms like CAF (conductive anodic filament growth). In other words, you should worry more about internal voltage strength of the PCB than of the molding, at least with standard FR4 PCB.
--- Updated ---

Internal horizontal PCB clearance requirements, IEC1010 versus IPC

Working Voltage [V]IEC61010 Table 8 [mm]IPC 2221 6.3.1 [mm]IEC V/milIPC V/mil
8000,1120320
10000,151,516917
12000,2215215
15000,32,7512714
20000,45411313
30000,86,59512
40001,298511
50001,511,58511
 
Last edited:

cdpstu

Newbie
Joined
Jul 2, 2021
Messages
2
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
21
i suggest you do consider the possibility of arcs between the PWB and the potting compound
i have seen a high voltage unit fail when it arced right along the boundary
between the transformer oil insulator and the fiberglass PWB

we ended up cutting a slot in the PWB, thereby lengthening the path, or forcing the arc to go through the oil
problem solved
Thanks! It does look like with these kind of potting and encapsulation techniques, you either do have very good insultation or it's failed and it's all gone - there's no in-between. I'll see if I can design in some slots so the epoxy is more like a barrier.
--- Updated ---

IEC 1010 is requiring 1.5 mm distance at 5 kV working voltage between conductors on the same layer for moulded and potted parts, the same as for inner PCB layers. Obviously, a homogenous interface between PCB and potting material is presumed.

It should be noted that IPC 2221 6.3 is suggesting a clearance as high as 11.5 mm at 5 kV for internal conductors. The numbers aren't substantiated in the standard. We can guess that they consider failure mechanisms like CAF (conductive anodic filament growth). In other words, you should worry more about internal voltage strength of the PCB than of the molding, at least with standard FR4 PCB.
--- Updated ---

Internal horizontal PCB clearance requirements, IEC1010 versus IPC

Working Voltage [V]IEC61010 Table 8 [mm]IPC 2221 6.3.1 [mm]IEC V/milIPC V/mil
8000,1120320
10000,151,516917
12000,2215215
15000,32,7512714
20000,45411313
30000,86,59512
40001,298511
50001,511,58511
Thanks for the help!

That is an incredible difference between the two standards, this is for a measurement system so it looks like we could push it into a very small package.

It's looking like creepage is no longer the problem and, as you say, I should be looking more into other failure modes such as breakdown/CAF.
 
Last edited:

Easy peasy

Advanced Member level 5
Joined
Aug 15, 2015
Messages
3,121
Helped
1,129
Reputation
2,258
Reaction score
1,180
Trophy points
113
Location
Melbourne
Activity points
17,165
the biggest issue is voids, all the E field concentrates over a void - if the material breaks down to SiO2, i.e glass, then the voltage withstand will be OK, if it breaks down to a carbon compound - then things tend to get worse ....
 

LaTeX Commands Quick-Menu:

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top