Sep 22, 2007 #1 gck Full Member level 3 Joined Oct 17, 2006 Messages 173 Helped 26 Reputation 52 Reaction score 19 Trophy points 1,298 Activity points 2,220 Pls tell me how to do post synthesis simulation using .edn file Thanks in advance
Sep 26, 2007 #2 K keano Member level 1 Joined Dec 24, 2004 Messages 36 Helped 1 Reputation 2 Reaction score 0 Trophy points 1,286 Location TUNISIA Activity points 251 The EDN file is used for place and route. To do a post synthesis simulation, you need to configure your synthesizer to output a VHDL or VERILOG file which you can use directly in your testbench.
The EDN file is used for place and route. To do a post synthesis simulation, you need to configure your synthesizer to output a VHDL or VERILOG file which you can use directly in your testbench.