dormant_bci
Newbie
Dear all
I've synthesized my design in DC and optimized for delay. According to the reports, there are no negative slack times, nor any time violations. But when I do the post-synthesis simulation in ModelSim, there are lots of setup and hold time violations.
My design has two clock domains but got separated using flip flops. In some flip-flops, I'm using the negative edge of the clock and in some others, I use the positive edge.
What causes this?
I've synthesized my design in DC and optimized for delay. According to the reports, there are no negative slack times, nor any time violations. But when I do the post-synthesis simulation in ModelSim, there are lots of setup and hold time violations.
My design has two clock domains but got separated using flip flops. In some flip-flops, I'm using the negative edge of the clock and in some others, I use the positive edge.
What causes this?