Tychus
Newbie level 5
Hi all,
I'm having problem with my design (fibonacci generator) i've been trying to fix this for the past few days in vain. I'm using Cadence RTL and Modelsim for the simulation. The netlist generated from this give no warnings or errors but still doesn't simulate right anyone can give some pointers ?
I'm having problem with my design (fibonacci generator) i've been trying to fix this for the past few days in vain. I'm using Cadence RTL and Modelsim for the simulation. The netlist generated from this give no warnings or errors but still doesn't simulate right anyone can give some pointers ?
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.all; entity fibonacci is port( clk, rst : in std_logic; limit : in std_logic_vector(9 downto 0); fibo_series: out std_logic_vector(9 downto 0) ); end fibonacci; architecture fibonacci of fibonacci is signal a,b,c : std_logic_vector(9 downto 0); begin process(clk,rst) begin if(rst = '1') then b <= std_logic_vector(to_unsigned(1, limit'length)); c <= std_logic_vector(to_unsigned(0, limit'length)); elsif(clk'event and clk='1') then if(c = limit) then b <= std_logic_vector(to_unsigned(1, limit'length)); c <= std_logic_vector(to_unsigned(0, limit'length)); else c<=b; b<=a; end if; end if; end process; a <= std_logic_vector(unsigned(b) + unsigned(c)); fibo_series <= c; end fibonacci;