post-synthesis Modelsim error

[arbalez]

i got this modelsim problem after simulating a post-synthesis design from quartusII. why does this happen? i've tried to change the resolution to 1 ps, 1 ns, and even 1 us, but still the simulation doesn't run properly. is this got to do with the vhdl design code and its testbench? or because of tool-related problem?

# ** Error: (vsim-3601) Iteration limit reached at time 0 us.
# ** Note: (vsim-3602) Delays were truncated during elaboration of the design.

thank you in advance.

 

[echo47]

Sounds like a bug in your testbench. Search the ModelSim User's Manual for the word "trunctated" or the phrase "iteration limit".

If you show us a small example, maybe someone can help you better.